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gen_ia32_new_nodes.c
1 #include "gen_ia32_new_nodes.h"
2 
3 #include "benode.h"
4 #include "ia32_bearch_t.h"
5 #include "gen_ia32_regalloc_if.h"
6 #include "ia32_new_nodes_t.h"
7 #include "fourcc.h"
8 #include "irgopt.h"
9 #include "ircons_t.h"
10 
11 ir_op *op_ia32_Adc = NULL;
12 ir_op *op_ia32_Add = NULL;
13 ir_op *op_ia32_AddMem = NULL;
14 ir_op *op_ia32_AddSP = NULL;
15 ir_op *op_ia32_Adds = NULL;
16 ir_op *op_ia32_And = NULL;
17 ir_op *op_ia32_AndMem = NULL;
18 ir_op *op_ia32_Andnp = NULL;
19 ir_op *op_ia32_Andp = NULL;
20 ir_op *op_ia32_Breakpoint = NULL;
21 ir_op *op_ia32_Bsf = NULL;
22 ir_op *op_ia32_Bsr = NULL;
23 ir_op *op_ia32_Bswap = NULL;
24 ir_op *op_ia32_Bswap16 = NULL;
25 ir_op *op_ia32_Bt = NULL;
26 ir_op *op_ia32_CMovcc = NULL;
27 ir_op *op_ia32_Call = NULL;
28 ir_op *op_ia32_ChangeCW = NULL;
29 ir_op *op_ia32_Cltd = NULL;
30 ir_op *op_ia32_Cmc = NULL;
31 ir_op *op_ia32_Cmp = NULL;
32 ir_op *op_ia32_CmpXChgMem = NULL;
33 ir_op *op_ia32_Const = NULL;
34 ir_op *op_ia32_Conv_FP2FP = NULL;
35 ir_op *op_ia32_Conv_FP2I = NULL;
36 ir_op *op_ia32_Conv_I2FP = NULL;
37 ir_op *op_ia32_Conv_I2I = NULL;
38 ir_op *op_ia32_CopyB = NULL;
39 ir_op *op_ia32_CopyB_i = NULL;
40 ir_op *op_ia32_CopyEbpEsp = NULL;
41 ir_op *op_ia32_CvtSI2SD = NULL;
42 ir_op *op_ia32_CvtSI2SS = NULL;
43 ir_op *op_ia32_Cwtl = NULL;
44 ir_op *op_ia32_Dec = NULL;
45 ir_op *op_ia32_DecMem = NULL;
46 ir_op *op_ia32_Div = NULL;
47 ir_op *op_ia32_Divs = NULL;
48 ir_op *op_ia32_Enter = NULL;
49 ir_op *op_ia32_FldCW = NULL;
50 ir_op *op_ia32_FnstCW = NULL;
51 ir_op *op_ia32_FnstCWNOP = NULL;
52 ir_op *op_ia32_FtstFnstsw = NULL;
53 ir_op *op_ia32_FucomFnstsw = NULL;
54 ir_op *op_ia32_Fucomi = NULL;
55 ir_op *op_ia32_FucomppFnstsw = NULL;
56 ir_op *op_ia32_GetEIP = NULL;
57 ir_op *op_ia32_IDiv = NULL;
58 ir_op *op_ia32_IJmp = NULL;
59 ir_op *op_ia32_IMul = NULL;
60 ir_op *op_ia32_IMul1OP = NULL;
61 ir_op *op_ia32_IMulImm = NULL;
62 ir_op *op_ia32_Immediate = NULL;
63 ir_op *op_ia32_Inc = NULL;
64 ir_op *op_ia32_IncMem = NULL;
65 ir_op *op_ia32_Inport = NULL;
66 ir_op *op_ia32_Jcc = NULL;
67 ir_op *op_ia32_Jmp = NULL;
68 ir_op *op_ia32_LdTls = NULL;
69 ir_op *op_ia32_Lea = NULL;
70 ir_op *op_ia32_Leave = NULL;
71 ir_op *op_ia32_Load = NULL;
72 ir_op *op_ia32_Maxs = NULL;
73 ir_op *op_ia32_Mins = NULL;
74 ir_op *op_ia32_Minus64 = NULL;
75 ir_op *op_ia32_Movd = NULL;
76 ir_op *op_ia32_Mul = NULL;
77 ir_op *op_ia32_Muls = NULL;
78 ir_op *op_ia32_Neg = NULL;
79 ir_op *op_ia32_NegMem = NULL;
80 ir_op *op_ia32_NoReg_FP = NULL;
81 ir_op *op_ia32_NoReg_GP = NULL;
82 ir_op *op_ia32_NoReg_XMM = NULL;
83 ir_op *op_ia32_Not = NULL;
84 ir_op *op_ia32_NotMem = NULL;
85 ir_op *op_ia32_Or = NULL;
86 ir_op *op_ia32_OrMem = NULL;
87 ir_op *op_ia32_Orp = NULL;
88 ir_op *op_ia32_Outport = NULL;
89 ir_op *op_ia32_Pop = NULL;
90 ir_op *op_ia32_PopMem = NULL;
91 ir_op *op_ia32_Popcnt = NULL;
92 ir_op *op_ia32_Prefetch = NULL;
93 ir_op *op_ia32_PrefetchNTA = NULL;
94 ir_op *op_ia32_PrefetchT0 = NULL;
95 ir_op *op_ia32_PrefetchT1 = NULL;
96 ir_op *op_ia32_PrefetchT2 = NULL;
97 ir_op *op_ia32_PrefetchW = NULL;
98 ir_op *op_ia32_Pslld = NULL;
99 ir_op *op_ia32_Psllq = NULL;
100 ir_op *op_ia32_Psrld = NULL;
101 ir_op *op_ia32_Push = NULL;
102 ir_op *op_ia32_PushEax = NULL;
103 ir_op *op_ia32_Ret = NULL;
104 ir_op *op_ia32_Rol = NULL;
105 ir_op *op_ia32_RolMem = NULL;
106 ir_op *op_ia32_Ror = NULL;
107 ir_op *op_ia32_RorMem = NULL;
108 ir_op *op_ia32_Sahf = NULL;
109 ir_op *op_ia32_Sar = NULL;
110 ir_op *op_ia32_SarMem = NULL;
111 ir_op *op_ia32_Sbb = NULL;
112 ir_op *op_ia32_Sbb0 = NULL;
113 ir_op *op_ia32_Setcc = NULL;
114 ir_op *op_ia32_SetccMem = NULL;
115 ir_op *op_ia32_Shl = NULL;
116 ir_op *op_ia32_ShlD = NULL;
117 ir_op *op_ia32_ShlMem = NULL;
118 ir_op *op_ia32_Shr = NULL;
119 ir_op *op_ia32_ShrD = NULL;
120 ir_op *op_ia32_ShrMem = NULL;
121 ir_op *op_ia32_Stc = NULL;
122 ir_op *op_ia32_Store = NULL;
123 ir_op *op_ia32_Sub = NULL;
124 ir_op *op_ia32_SubMem = NULL;
125 ir_op *op_ia32_SubSP = NULL;
126 ir_op *op_ia32_Subs = NULL;
127 ir_op *op_ia32_SwitchJmp = NULL;
128 ir_op *op_ia32_Test = NULL;
129 ir_op *op_ia32_UD2 = NULL;
130 ir_op *op_ia32_Ucomis = NULL;
131 ir_op *op_ia32_Xor = NULL;
132 ir_op *op_ia32_Xor0 = NULL;
133 ir_op *op_ia32_XorHighLow = NULL;
134 ir_op *op_ia32_XorMem = NULL;
135 ir_op *op_ia32_Xorp = NULL;
136 ir_op *op_ia32_emms = NULL;
137 ir_op *op_ia32_fabs = NULL;
138 ir_op *op_ia32_fadd = NULL;
139 ir_op *op_ia32_fchs = NULL;
140 ir_op *op_ia32_fdiv = NULL;
141 ir_op *op_ia32_fdup = NULL;
142 ir_op *op_ia32_femms = NULL;
143 ir_op *op_ia32_ffreep = NULL;
144 ir_op *op_ia32_fild = NULL;
145 ir_op *op_ia32_fist = NULL;
146 ir_op *op_ia32_fistp = NULL;
147 ir_op *op_ia32_fisttp = NULL;
148 ir_op *op_ia32_fld = NULL;
149 ir_op *op_ia32_fld1 = NULL;
150 ir_op *op_ia32_fldl2e = NULL;
151 ir_op *op_ia32_fldl2t = NULL;
152 ir_op *op_ia32_fldlg2 = NULL;
153 ir_op *op_ia32_fldln2 = NULL;
154 ir_op *op_ia32_fldpi = NULL;
155 ir_op *op_ia32_fldz = NULL;
156 ir_op *op_ia32_fmul = NULL;
157 ir_op *op_ia32_fpop = NULL;
158 ir_op *op_ia32_fst = NULL;
159 ir_op *op_ia32_fstp = NULL;
160 ir_op *op_ia32_fsub = NULL;
161 ir_op *op_ia32_fxch = NULL;
162 ir_op *op_ia32_l_Adc = NULL;
163 ir_op *op_ia32_l_Add = NULL;
164 ir_op *op_ia32_l_FloattoLL = NULL;
165 ir_op *op_ia32_l_IMul = NULL;
166 ir_op *op_ia32_l_LLtoFloat = NULL;
167 ir_op *op_ia32_l_Minus64 = NULL;
168 ir_op *op_ia32_l_Mul = NULL;
169 ir_op *op_ia32_l_Sbb = NULL;
170 ir_op *op_ia32_l_Sub = NULL;
171 ir_op *op_ia32_xAllOnes = NULL;
172 ir_op *op_ia32_xLoad = NULL;
173 ir_op *op_ia32_xPzero = NULL;
174 ir_op *op_ia32_xStore = NULL;
175 ir_op *op_ia32_xZero = NULL;
176 ir_op *op_ia32_xxLoad = NULL;
177 ir_op *op_ia32_xxStore = NULL;
178 
179 
180 static int ia32_opcode_start = -1;
181 
183 #define ia32_op_tag FOURCC('i', 'a', '3', '2')
184 
186 int is_ia32_op(const ir_op *op)
187 {
188  return get_op_tag(op) == ia32_op_tag;
189 }
190 
192 int is_ia32_irn(const ir_node *node)
193 {
194  return is_ia32_op(get_irn_op(node));
195 }
196 
197 int get_ia32_irn_opcode(const ir_node *node)
198 {
199  assert(is_ia32_irn(node));
200  return get_irn_opcode(node) - ia32_opcode_start;
201 }
202 
203 #undef BIT
204 #define BIT(x) (1 << (x))
205 
206 static const unsigned ia32_limit_gp_eax_ebx_ecx_edx[] = { BIT(REG_GP_EAX) | BIT(REG_GP_EBX) | BIT(REG_GP_ECX) | BIT(REG_GP_EDX), 0 };
207 static const unsigned ia32_limit_gp_esp[] = { BIT(REG_GP_ESP), 0 };
208 static const unsigned ia32_limit_gp_gp_NOREG[] = { BIT(REG_GP_GP_NOREG), 0 };
209 static const unsigned ia32_limit_gp_ebp[] = { BIT(REG_GP_EBP), 0 };
210 static const unsigned ia32_limit_fp_fp_NOREG[] = { BIT(REG_FP_FP_NOREG), 0 };
211 static const unsigned ia32_limit_xmm_xmm_NOREG[] = { BIT(REG_XMM_XMM_NOREG), 0 };
212 
213 static const arch_register_req_t ia32_requirements_gp_in_r3_in_r4 = {
214  .cls = &ia32_reg_classes[CLASS_ia32_gp],
215  .limited = NULL,
216  .should_be_same = 24,
217  .must_be_different = 0,
218  .width = 1,
219 };
220 
221 static const arch_register_req_t ia32_requirements_gp_eax_ebx_ecx_edx = {
222  .cls = &ia32_reg_classes[CLASS_ia32_gp],
223  .limited = ia32_limit_gp_eax_ebx_ecx_edx,
224  .should_be_same = 0,
225  .must_be_different = 0,
226  .width = 1,
227 };
228 
229 static const arch_register_req_t ia32_requirements_gp_eax_ebx_ecx_edx_in_r3_in_r4 = {
230  .cls = &ia32_reg_classes[CLASS_ia32_gp],
231  .limited = ia32_limit_gp_eax_ebx_ecx_edx,
232  .should_be_same = 24,
233  .must_be_different = 0,
234  .width = 1,
235 };
236 
237 static const arch_register_req_t ia32_requirements_gp_esp_I = {
238  .cls = &ia32_reg_classes[CLASS_ia32_gp],
239  .limited = ia32_limit_gp_esp,
240  .should_be_same = 0,
241  .must_be_different = 0,
242  .width = 1,
243  .ignore = true,
244 };
245 
246 static const arch_register_req_t ia32_requirements_xmm_in_r3_in_r4 = {
247  .cls = &ia32_reg_classes[CLASS_ia32_xmm],
248  .limited = NULL,
249  .should_be_same = 24,
250  .must_be_different = 0,
251  .width = 1,
252 };
253 
254 static const arch_register_req_t ia32_requirements_xmm_in_r3_not_in_r4 = {
255  .cls = &ia32_reg_classes[CLASS_ia32_xmm],
256  .limited = NULL,
257  .should_be_same = 8,
258  .must_be_different = 16,
259  .width = 1,
260 };
261 
262 static const arch_register_req_t ia32_requirements_gp_in_r0 = {
263  .cls = &ia32_reg_classes[CLASS_ia32_gp],
264  .limited = NULL,
265  .should_be_same = 1,
266  .must_be_different = 0,
267  .width = 1,
268 };
269 
270 static const arch_register_req_t ia32_requirements_gp_eax_ebx_ecx_edx_in_r0 = {
271  .cls = &ia32_reg_classes[CLASS_ia32_gp],
272  .limited = ia32_limit_gp_eax_ebx_ecx_edx,
273  .should_be_same = 1,
274  .must_be_different = 0,
275  .width = 1,
276 };
277 
278 static const arch_register_req_t ia32_requirements_gp_gp_NOREG_I = {
279  .cls = &ia32_reg_classes[CLASS_ia32_gp],
280  .limited = ia32_limit_gp_gp_NOREG,
281  .should_be_same = 0,
282  .must_be_different = 0,
283  .width = 1,
284  .ignore = true,
285 };
286 
287 static const arch_register_req_t ia32_requirements_gp_ebp_I = {
288  .cls = &ia32_reg_classes[CLASS_ia32_gp],
289  .limited = ia32_limit_gp_ebp,
290  .should_be_same = 0,
291  .must_be_different = 0,
292  .width = 1,
293  .ignore = true,
294 };
295 
296 static const arch_register_req_t ia32_requirements_gp_in_r1 = {
297  .cls = &ia32_reg_classes[CLASS_ia32_gp],
298  .limited = NULL,
299  .should_be_same = 2,
300  .must_be_different = 0,
301  .width = 1,
302 };
303 
304 static const arch_register_req_t ia32_requirements_fp_fp_NOREG_I = {
305  .cls = &ia32_reg_classes[CLASS_ia32_fp],
306  .limited = ia32_limit_fp_fp_NOREG,
307  .should_be_same = 0,
308  .must_be_different = 0,
309  .width = 1,
310  .ignore = true,
311 };
312 
313 static const arch_register_req_t ia32_requirements_xmm_xmm_NOREG_I = {
314  .cls = &ia32_reg_classes[CLASS_ia32_xmm],
315  .limited = ia32_limit_xmm_xmm_NOREG,
316  .should_be_same = 0,
317  .must_be_different = 0,
318  .width = 1,
319  .ignore = true,
320 };
321 
322 static const arch_register_req_t ia32_requirements_xmm_in_r0_not_in_r1 = {
323  .cls = &ia32_reg_classes[CLASS_ia32_xmm],
324  .limited = NULL,
325  .should_be_same = 1,
326  .must_be_different = 2,
327  .width = 1,
328 };
329 
330 static const arch_register_req_t ia32_requirements_gp_in_r0_not_in_r1 = {
331  .cls = &ia32_reg_classes[CLASS_ia32_gp],
332  .limited = NULL,
333  .should_be_same = 1,
334  .must_be_different = 2,
335  .width = 1,
336 };
337 
338 static const arch_register_req_t ia32_requirements_gp_in_r3 = {
339  .cls = &ia32_reg_classes[CLASS_ia32_gp],
340  .limited = NULL,
341  .should_be_same = 8,
342  .must_be_different = 0,
343  .width = 1,
344 };
345 
346 static const arch_register_req_t ia32_requirements_gp_in_r0_not_in_r1_not_in_r2 = {
347  .cls = &ia32_reg_classes[CLASS_ia32_gp],
348  .limited = NULL,
349  .should_be_same = 1,
350  .must_be_different = 6,
351  .width = 1,
352 };
353 
354 static const arch_register_req_t ia32_requirements_gp_in_r0_in_r1 = {
355  .cls = &ia32_reg_classes[CLASS_ia32_gp],
356  .limited = NULL,
357  .should_be_same = 3,
358  .must_be_different = 0,
359  .width = 1,
360 };
361 
362 static const arch_register_req_t ia32_requirements_gp_eax_ebx_ecx_edx_in_r3 = {
363  .cls = &ia32_reg_classes[CLASS_ia32_gp],
364  .limited = ia32_limit_gp_eax_ebx_ecx_edx,
365  .should_be_same = 8,
366  .must_be_different = 0,
367  .width = 1,
368 };
369 
370 static const arch_register_req_t ia32_requirements_xmm_in_r3 = {
371  .cls = &ia32_reg_classes[CLASS_ia32_xmm],
372  .limited = NULL,
373  .should_be_same = 8,
374  .must_be_different = 0,
375  .width = 1,
376 };
377 
378 static const arch_register_req_t ia32_requirements_fp_fp_K = {
379  .cls = &ia32_reg_classes[CLASS_ia32_fp],
380  .width = 1,
381  .kills_value = true,
382 };
383 
384 
385 
386 ir_node *new_bd_ia32_Adc(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, ir_node *eflags, x86_insn_size_t size)
387 {
388  static arch_register_req_t const *in_reqs[] = {
389  &ia32_class_reg_req_gp,
390  &ia32_class_reg_req_gp,
391  &arch_memory_requirement,
392  &ia32_class_reg_req_gp,
393  &ia32_class_reg_req_gp,
394  &ia32_class_reg_req_flags,
395  };
396 
397  /* construct in array */
398  ir_node *const in[] = {
399  base,
400  index,
401  mem,
402  left,
403  right,
404  eflags,
405  };
406 
407  ir_graph *const irg = get_irn_irg(block);
408  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Adc, ia32_mode_gp, 6, in);
409 
410  /* init node attributes */
411 
412  /* flags */
413  arch_irn_flags_t irn_flags = arch_irn_flags_none;
414  irn_flags |= arch_irn_flag_modify_flags;
415  int const n_res = 3;
416  be_info_init_irn(res, irn_flags, in_reqs, n_res);
417  ia32_condcode_attr_t *const attr = (ia32_condcode_attr_t*)get_irn_generic_attr(res);
418  (void)attr; /* avoid potential warning */
419  x86_condition_code_t condition_code = x86_cc_carry;
420  init_ia32_attributes(res, size);
421  init_ia32_condcode_attributes(res, condition_code);
422  set_ia32_am_support(res, ia32_am_binary);
423  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
424  out_infos[0].req = &ia32_requirements_gp_in_r3_in_r4;
425  out_infos[1].req = &ia32_class_reg_req_flags;
426  out_infos[2].req = &arch_memory_requirement;
427 
428  verify_new_node(res);
429  return optimize_node(res);
430 }
431 
432 ir_node *new_bd_ia32_Add(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size)
433 {
434  static arch_register_req_t const *in_reqs[] = {
435  &ia32_class_reg_req_gp,
436  &ia32_class_reg_req_gp,
437  &arch_memory_requirement,
438  &ia32_class_reg_req_gp,
439  &ia32_class_reg_req_gp,
440  };
441 
442  /* construct in array */
443  ir_node *const in[] = {
444  base,
445  index,
446  mem,
447  left,
448  right,
449  };
450 
451  ir_graph *const irg = get_irn_irg(block);
452  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Add, ia32_mode_gp, 5, in);
453 
454  /* init node attributes */
455 
456  /* flags */
457  arch_irn_flags_t irn_flags = arch_irn_flags_none;
458  irn_flags |= arch_irn_flag_modify_flags;
459  irn_flags |= arch_irn_flag_rematerializable;
460  int const n_res = 3;
461  be_info_init_irn(res, irn_flags, in_reqs, n_res);
462  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
463  (void)attr; /* avoid potential warning */
464  init_ia32_attributes(res, size);
465  set_ia32_am_support(res, ia32_am_binary);
466  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
467  out_infos[0].req = &ia32_requirements_gp_in_r3_in_r4;
468  out_infos[1].req = &ia32_class_reg_req_flags;
469  out_infos[2].req = &arch_memory_requirement;
470 
471  verify_new_node(res);
472  return optimize_node(res);
473 }
474 
475 ir_node *new_bd_ia32_Add_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size)
476 {
477  static arch_register_req_t const *in_reqs[] = {
478  &ia32_class_reg_req_gp,
479  &ia32_class_reg_req_gp,
480  &arch_memory_requirement,
481  &ia32_requirements_gp_eax_ebx_ecx_edx,
482  &ia32_requirements_gp_eax_ebx_ecx_edx,
483  };
484 
485  /* construct in array */
486  ir_node *const in[] = {
487  base,
488  index,
489  mem,
490  left,
491  right,
492  };
493 
494  ir_graph *const irg = get_irn_irg(block);
495  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Add, ia32_mode_gp, 5, in);
496 
497  /* init node attributes */
498 
499  /* flags */
500  arch_irn_flags_t irn_flags = arch_irn_flags_none;
501  irn_flags |= arch_irn_flag_modify_flags;
502  irn_flags |= arch_irn_flag_rematerializable;
503  int const n_res = 3;
504  be_info_init_irn(res, irn_flags, in_reqs, n_res);
505  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
506  (void)attr; /* avoid potential warning */
507  init_ia32_attributes(res, size);
508  set_ia32_am_support(res, ia32_am_binary);
509  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
510  out_infos[0].req = &ia32_requirements_gp_eax_ebx_ecx_edx_in_r3_in_r4;
511  out_infos[1].req = &ia32_class_reg_req_flags;
512  out_infos[2].req = &arch_memory_requirement;
513 
514  verify_new_node(res);
515  return optimize_node(res);
516 }
517 
518 ir_node *new_bd_ia32_AddMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size)
519 {
520  static arch_register_req_t const *in_reqs[] = {
521  &ia32_class_reg_req_gp,
522  &ia32_class_reg_req_gp,
523  &arch_memory_requirement,
524  &ia32_class_reg_req_gp,
525  };
526 
527  /* construct in array */
528  ir_node *const in[] = {
529  base,
530  index,
531  mem,
532  val,
533  };
534 
535  ir_graph *const irg = get_irn_irg(block);
536  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_AddMem, mode_T, 4, in);
537 
538  /* init node attributes */
539 
540  /* flags */
541  arch_irn_flags_t irn_flags = arch_irn_flags_none;
542  irn_flags |= arch_irn_flag_modify_flags;
543  irn_flags |= arch_irn_flag_rematerializable;
544  int const n_res = 3;
545  be_info_init_irn(res, irn_flags, in_reqs, n_res);
546  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
547  (void)attr; /* avoid potential warning */
548  init_ia32_attributes(res, size);
549  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
550  out_infos[0].req = &arch_no_requirement;
551  out_infos[1].req = &ia32_class_reg_req_flags;
552  out_infos[2].req = &arch_memory_requirement;
553 
554  verify_new_node(res);
555  return optimize_node(res);
556 }
557 
558 ir_node *new_bd_ia32_AddMem_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size)
559 {
560  static arch_register_req_t const *in_reqs[] = {
561  &ia32_class_reg_req_gp,
562  &ia32_class_reg_req_gp,
563  &arch_memory_requirement,
564  &ia32_requirements_gp_eax_ebx_ecx_edx,
565  };
566 
567  /* construct in array */
568  ir_node *const in[] = {
569  base,
570  index,
571  mem,
572  val,
573  };
574 
575  ir_graph *const irg = get_irn_irg(block);
576  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_AddMem, mode_T, 4, in);
577 
578  /* init node attributes */
579 
580  /* flags */
581  arch_irn_flags_t irn_flags = arch_irn_flags_none;
582  irn_flags |= arch_irn_flag_modify_flags;
583  irn_flags |= arch_irn_flag_rematerializable;
584  int const n_res = 3;
585  be_info_init_irn(res, irn_flags, in_reqs, n_res);
586  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
587  (void)attr; /* avoid potential warning */
588  init_ia32_attributes(res, size);
589  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
590  out_infos[0].req = &arch_no_requirement;
591  out_infos[1].req = &ia32_class_reg_req_flags;
592  out_infos[2].req = &arch_memory_requirement;
593 
594  verify_new_node(res);
595  return optimize_node(res);
596 }
597 
598 ir_node *new_bd_ia32_AddSP(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *stack, ir_node *amount)
599 {
600  static arch_register_req_t const *in_reqs[] = {
601  &ia32_class_reg_req_gp,
602  &ia32_class_reg_req_gp,
603  &arch_memory_requirement,
604  &ia32_single_reg_req_gp_esp,
605  &ia32_class_reg_req_gp,
606  };
607 
608  /* construct in array */
609  ir_node *const in[] = {
610  base,
611  index,
612  mem,
613  stack,
614  amount,
615  };
616 
617  ir_graph *const irg = get_irn_irg(block);
618  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_AddSP, mode_T, 5, in);
619 
620  /* init node attributes */
621 
622  /* flags */
623  arch_irn_flags_t irn_flags = arch_irn_flags_none;
624  irn_flags |= arch_irn_flag_modify_flags;
625  int const n_res = 2;
626  be_info_init_irn(res, irn_flags, in_reqs, n_res);
627  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
628  (void)attr; /* avoid potential warning */
629  x86_insn_size_t const size = X86_SIZE_32;
630  init_ia32_attributes(res, size);
631  set_ia32_am_support(res, ia32_am_binary);
632  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
633  out_infos[0].req = &ia32_requirements_gp_esp_I;
634  out_infos[1].req = &arch_memory_requirement;
635 
636  verify_new_node(res);
637  return optimize_node(res);
638 }
639 
640 ir_node *new_bd_ia32_Adds(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size)
641 {
642  static arch_register_req_t const *in_reqs[] = {
643  &ia32_class_reg_req_gp,
644  &ia32_class_reg_req_gp,
645  &arch_memory_requirement,
646  &ia32_class_reg_req_xmm,
647  &ia32_class_reg_req_xmm,
648  };
649 
650  /* construct in array */
651  ir_node *const in[] = {
652  base,
653  index,
654  mem,
655  left,
656  right,
657  };
658 
659  ir_graph *const irg = get_irn_irg(block);
660  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Adds, ia32_mode_float64, 5, in);
661 
662  /* init node attributes */
663 
664  /* flags */
665  arch_irn_flags_t irn_flags = arch_irn_flags_none;
666  irn_flags |= arch_irn_flag_rematerializable;
667  int const n_res = 3;
668  be_info_init_irn(res, irn_flags, in_reqs, n_res);
669  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
670  (void)attr; /* avoid potential warning */
671  init_ia32_attributes(res, size);
672  set_ia32_am_support(res, ia32_am_binary);
673  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
674  out_infos[0].req = &ia32_requirements_xmm_in_r3_in_r4;
675  out_infos[1].req = &ia32_class_reg_req_flags;
676  out_infos[2].req = &arch_memory_requirement;
677 
678  verify_new_node(res);
679  return optimize_node(res);
680 }
681 
682 ir_node *new_bd_ia32_And(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size)
683 {
684  static arch_register_req_t const *in_reqs[] = {
685  &ia32_class_reg_req_gp,
686  &ia32_class_reg_req_gp,
687  &arch_memory_requirement,
688  &ia32_class_reg_req_gp,
689  &ia32_class_reg_req_gp,
690  };
691 
692  /* construct in array */
693  ir_node *const in[] = {
694  base,
695  index,
696  mem,
697  left,
698  right,
699  };
700 
701  ir_graph *const irg = get_irn_irg(block);
702  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_And, ia32_mode_gp, 5, in);
703 
704  /* init node attributes */
705 
706  /* flags */
707  arch_irn_flags_t irn_flags = arch_irn_flags_none;
708  irn_flags |= arch_irn_flag_modify_flags;
709  irn_flags |= arch_irn_flag_rematerializable;
710  int const n_res = 3;
711  be_info_init_irn(res, irn_flags, in_reqs, n_res);
712  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
713  (void)attr; /* avoid potential warning */
714  init_ia32_attributes(res, size);
715  set_ia32_am_support(res, ia32_am_binary);
716  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
717  out_infos[0].req = &ia32_requirements_gp_in_r3_in_r4;
718  out_infos[1].req = &ia32_class_reg_req_flags;
719  out_infos[2].req = &arch_memory_requirement;
720 
721  verify_new_node(res);
722  return optimize_node(res);
723 }
724 
725 ir_node *new_bd_ia32_And_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size)
726 {
727  static arch_register_req_t const *in_reqs[] = {
728  &ia32_class_reg_req_gp,
729  &ia32_class_reg_req_gp,
730  &arch_memory_requirement,
731  &ia32_requirements_gp_eax_ebx_ecx_edx,
732  &ia32_requirements_gp_eax_ebx_ecx_edx,
733  };
734 
735  /* construct in array */
736  ir_node *const in[] = {
737  base,
738  index,
739  mem,
740  left,
741  right,
742  };
743 
744  ir_graph *const irg = get_irn_irg(block);
745  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_And, ia32_mode_gp, 5, in);
746 
747  /* init node attributes */
748 
749  /* flags */
750  arch_irn_flags_t irn_flags = arch_irn_flags_none;
751  irn_flags |= arch_irn_flag_modify_flags;
752  irn_flags |= arch_irn_flag_rematerializable;
753  int const n_res = 3;
754  be_info_init_irn(res, irn_flags, in_reqs, n_res);
755  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
756  (void)attr; /* avoid potential warning */
757  init_ia32_attributes(res, size);
758  set_ia32_am_support(res, ia32_am_binary);
759  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
760  out_infos[0].req = &ia32_requirements_gp_eax_ebx_ecx_edx_in_r3_in_r4;
761  out_infos[1].req = &ia32_class_reg_req_flags;
762  out_infos[2].req = &arch_memory_requirement;
763 
764  verify_new_node(res);
765  return optimize_node(res);
766 }
767 
768 ir_node *new_bd_ia32_AndMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size)
769 {
770  static arch_register_req_t const *in_reqs[] = {
771  &ia32_class_reg_req_gp,
772  &ia32_class_reg_req_gp,
773  &arch_memory_requirement,
774  &ia32_class_reg_req_gp,
775  };
776 
777  /* construct in array */
778  ir_node *const in[] = {
779  base,
780  index,
781  mem,
782  val,
783  };
784 
785  ir_graph *const irg = get_irn_irg(block);
786  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_AndMem, mode_T, 4, in);
787 
788  /* init node attributes */
789 
790  /* flags */
791  arch_irn_flags_t irn_flags = arch_irn_flags_none;
792  irn_flags |= arch_irn_flag_modify_flags;
793  irn_flags |= arch_irn_flag_rematerializable;
794  int const n_res = 3;
795  be_info_init_irn(res, irn_flags, in_reqs, n_res);
796  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
797  (void)attr; /* avoid potential warning */
798  init_ia32_attributes(res, size);
799  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
800  out_infos[0].req = &arch_no_requirement;
801  out_infos[1].req = &ia32_class_reg_req_flags;
802  out_infos[2].req = &arch_memory_requirement;
803 
804  verify_new_node(res);
805  return optimize_node(res);
806 }
807 
808 ir_node *new_bd_ia32_AndMem_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size)
809 {
810  static arch_register_req_t const *in_reqs[] = {
811  &ia32_class_reg_req_gp,
812  &ia32_class_reg_req_gp,
813  &arch_memory_requirement,
814  &ia32_requirements_gp_eax_ebx_ecx_edx,
815  };
816 
817  /* construct in array */
818  ir_node *const in[] = {
819  base,
820  index,
821  mem,
822  val,
823  };
824 
825  ir_graph *const irg = get_irn_irg(block);
826  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_AndMem, mode_T, 4, in);
827 
828  /* init node attributes */
829 
830  /* flags */
831  arch_irn_flags_t irn_flags = arch_irn_flags_none;
832  irn_flags |= arch_irn_flag_modify_flags;
833  irn_flags |= arch_irn_flag_rematerializable;
834  int const n_res = 3;
835  be_info_init_irn(res, irn_flags, in_reqs, n_res);
836  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
837  (void)attr; /* avoid potential warning */
838  init_ia32_attributes(res, size);
839  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
840  out_infos[0].req = &arch_no_requirement;
841  out_infos[1].req = &ia32_class_reg_req_flags;
842  out_infos[2].req = &arch_memory_requirement;
843 
844  verify_new_node(res);
845  return optimize_node(res);
846 }
847 
848 ir_node *new_bd_ia32_Andnp(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size)
849 {
850  static arch_register_req_t const *in_reqs[] = {
851  &ia32_class_reg_req_gp,
852  &ia32_class_reg_req_gp,
853  &arch_memory_requirement,
854  &ia32_class_reg_req_xmm,
855  &ia32_class_reg_req_xmm,
856  };
857 
858  /* construct in array */
859  ir_node *const in[] = {
860  base,
861  index,
862  mem,
863  left,
864  right,
865  };
866 
867  ir_graph *const irg = get_irn_irg(block);
868  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Andnp, ia32_mode_float64, 5, in);
869 
870  /* init node attributes */
871 
872  /* flags */
873  arch_irn_flags_t irn_flags = arch_irn_flags_none;
874  irn_flags |= arch_irn_flag_rematerializable;
875  int const n_res = 3;
876  be_info_init_irn(res, irn_flags, in_reqs, n_res);
877  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
878  (void)attr; /* avoid potential warning */
879  init_ia32_attributes(res, size);
880  set_ia32_am_support(res, ia32_am_binary);
881  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
882  out_infos[0].req = &ia32_requirements_xmm_in_r3_not_in_r4;
883  out_infos[1].req = &ia32_class_reg_req_flags;
884  out_infos[2].req = &arch_memory_requirement;
885 
886  verify_new_node(res);
887  return optimize_node(res);
888 }
889 
890 ir_node *new_bd_ia32_Andp(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size)
891 {
892  static arch_register_req_t const *in_reqs[] = {
893  &ia32_class_reg_req_gp,
894  &ia32_class_reg_req_gp,
895  &arch_memory_requirement,
896  &ia32_class_reg_req_xmm,
897  &ia32_class_reg_req_xmm,
898  };
899 
900  /* construct in array */
901  ir_node *const in[] = {
902  base,
903  index,
904  mem,
905  left,
906  right,
907  };
908 
909  ir_graph *const irg = get_irn_irg(block);
910  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Andp, ia32_mode_float64, 5, in);
911 
912  /* init node attributes */
913 
914  /* flags */
915  arch_irn_flags_t irn_flags = arch_irn_flags_none;
916  irn_flags |= arch_irn_flag_rematerializable;
917  int const n_res = 3;
918  be_info_init_irn(res, irn_flags, in_reqs, n_res);
919  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
920  (void)attr; /* avoid potential warning */
921  init_ia32_attributes(res, size);
922  set_ia32_am_support(res, ia32_am_binary);
923  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
924  out_infos[0].req = &ia32_requirements_xmm_in_r3_in_r4;
925  out_infos[1].req = &ia32_class_reg_req_flags;
926  out_infos[2].req = &arch_memory_requirement;
927 
928  verify_new_node(res);
929  return optimize_node(res);
930 }
931 
932 ir_node *new_bd_ia32_Breakpoint(dbg_info *dbgi, ir_node *block, ir_node *mem)
933 {
934  static arch_register_req_t const *in_reqs[] = {
935  &arch_memory_requirement,
936  };
937 
938  /* construct in array */
939  ir_node *const in[] = {
940  mem,
941  };
942 
943  ir_graph *const irg = get_irn_irg(block);
944  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Breakpoint, mode_M, 1, in);
945 
946  /* init node attributes */
947 
948  /* flags */
949  arch_irn_flags_t irn_flags = arch_irn_flags_none;
950  int const n_res = 1;
951  be_info_init_irn(res, irn_flags, in_reqs, n_res);
952  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
953  (void)attr; /* avoid potential warning */
954  x86_insn_size_t const size = X86_SIZE_32;
955  init_ia32_attributes(res, size);
956  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
957  out_infos[0].req = &arch_memory_requirement;
958 
959  verify_new_node(res);
960  return optimize_node(res);
961 }
962 
963 ir_node *new_bd_ia32_Bsf(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *operand, x86_insn_size_t size)
964 {
965  static arch_register_req_t const *in_reqs[] = {
966  &ia32_class_reg_req_gp,
967  &ia32_class_reg_req_gp,
968  &arch_memory_requirement,
969  &ia32_class_reg_req_gp,
970  };
971 
972  /* construct in array */
973  ir_node *const in[] = {
974  base,
975  index,
976  mem,
977  operand,
978  };
979 
980  ir_graph *const irg = get_irn_irg(block);
981  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Bsf, ia32_mode_gp, 4, in);
982 
983  /* init node attributes */
984 
985  /* flags */
986  arch_irn_flags_t irn_flags = arch_irn_flags_none;
987  irn_flags |= arch_irn_flag_modify_flags;
988  irn_flags |= arch_irn_flag_rematerializable;
989  int const n_res = 3;
990  be_info_init_irn(res, irn_flags, in_reqs, n_res);
991  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
992  (void)attr; /* avoid potential warning */
993  init_ia32_attributes(res, size);
994  set_ia32_am_support(res, ia32_am_unary);
995  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
996  out_infos[0].req = &ia32_class_reg_req_gp;
997  out_infos[1].req = &ia32_class_reg_req_flags;
998  out_infos[2].req = &arch_memory_requirement;
999 
1000  verify_new_node(res);
1001  return optimize_node(res);
1002 }
1003 
1004 ir_node *new_bd_ia32_Bsr(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *operand, x86_insn_size_t size)
1005 {
1006  static arch_register_req_t const *in_reqs[] = {
1007  &ia32_class_reg_req_gp,
1008  &ia32_class_reg_req_gp,
1009  &arch_memory_requirement,
1010  &ia32_class_reg_req_gp,
1011  };
1012 
1013  /* construct in array */
1014  ir_node *const in[] = {
1015  base,
1016  index,
1017  mem,
1018  operand,
1019  };
1020 
1021  ir_graph *const irg = get_irn_irg(block);
1022  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Bsr, ia32_mode_gp, 4, in);
1023 
1024  /* init node attributes */
1025 
1026  /* flags */
1027  arch_irn_flags_t irn_flags = arch_irn_flags_none;
1028  irn_flags |= arch_irn_flag_modify_flags;
1029  irn_flags |= arch_irn_flag_rematerializable;
1030  int const n_res = 3;
1031  be_info_init_irn(res, irn_flags, in_reqs, n_res);
1032  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
1033  (void)attr; /* avoid potential warning */
1034  init_ia32_attributes(res, size);
1035  set_ia32_am_support(res, ia32_am_unary);
1036  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
1037  out_infos[0].req = &ia32_class_reg_req_gp;
1038  out_infos[1].req = &ia32_class_reg_req_flags;
1039  out_infos[2].req = &arch_memory_requirement;
1040 
1041  verify_new_node(res);
1042  return optimize_node(res);
1043 }
1044 
1045 ir_node *new_bd_ia32_Bswap(dbg_info *dbgi, ir_node *block, ir_node *val, x86_insn_size_t size)
1046 {
1047  static arch_register_req_t const *in_reqs[] = {
1048  &ia32_class_reg_req_gp,
1049  };
1050 
1051  /* construct in array */
1052  ir_node *const in[] = {
1053  val,
1054  };
1055 
1056  ir_graph *const irg = get_irn_irg(block);
1057  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Bswap, ia32_mode_gp, 1, in);
1058 
1059  /* init node attributes */
1060 
1061  /* flags */
1062  arch_irn_flags_t irn_flags = arch_irn_flags_none;
1063  irn_flags |= arch_irn_flag_rematerializable;
1064  int const n_res = 1;
1065  be_info_init_irn(res, irn_flags, in_reqs, n_res);
1066  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
1067  (void)attr; /* avoid potential warning */
1068  init_ia32_attributes(res, size);
1069  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
1070  out_infos[0].req = &ia32_requirements_gp_in_r0;
1071 
1072  verify_new_node(res);
1073  return optimize_node(res);
1074 }
1075 
1076 ir_node *new_bd_ia32_Bswap16(dbg_info *dbgi, ir_node *block, ir_node *val)
1077 {
1078  static arch_register_req_t const *in_reqs[] = {
1079  &ia32_requirements_gp_eax_ebx_ecx_edx,
1080  };
1081 
1082  /* construct in array */
1083  ir_node *const in[] = {
1084  val,
1085  };
1086 
1087  ir_graph *const irg = get_irn_irg(block);
1088  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Bswap16, ia32_mode_gp, 1, in);
1089 
1090  /* init node attributes */
1091 
1092  /* flags */
1093  arch_irn_flags_t irn_flags = arch_irn_flags_none;
1094  irn_flags |= arch_irn_flag_rematerializable;
1095  int const n_res = 1;
1096  be_info_init_irn(res, irn_flags, in_reqs, n_res);
1097  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
1098  (void)attr; /* avoid potential warning */
1099  x86_insn_size_t const size = X86_SIZE_8;
1100  init_ia32_attributes(res, size);
1101  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
1102  out_infos[0].req = &ia32_requirements_gp_eax_ebx_ecx_edx_in_r0;
1103 
1104  verify_new_node(res);
1105  return optimize_node(res);
1106 }
1107 
1108 ir_node *new_bd_ia32_Bt(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, x86_insn_size_t size)
1109 {
1110  static arch_register_req_t const *in_reqs[] = {
1111  &ia32_class_reg_req_gp,
1112  &ia32_class_reg_req_gp,
1113  };
1114 
1115  /* construct in array */
1116  ir_node *const in[] = {
1117  left,
1118  right,
1119  };
1120 
1121  ir_graph *const irg = get_irn_irg(block);
1122  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Bt, ia32_mode_flags, 2, in);
1123 
1124  /* init node attributes */
1125 
1126  /* flags */
1127  arch_irn_flags_t irn_flags = arch_irn_flags_none;
1128  irn_flags |= arch_irn_flag_modify_flags;
1129  irn_flags |= arch_irn_flag_rematerializable;
1130  int const n_res = 1;
1131  be_info_init_irn(res, irn_flags, in_reqs, n_res);
1132  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
1133  (void)attr; /* avoid potential warning */
1134  init_ia32_attributes(res, size);
1135  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
1136  out_infos[0].req = &ia32_class_reg_req_flags;
1137 
1138  verify_new_node(res);
1139  return optimize_node(res);
1140 }
1141 
1142 ir_node *new_bd_ia32_CMovcc(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val_false, ir_node *val_true, ir_node *eflags, x86_insn_size_t size, x86_condition_code_t condition_code)
1143 {
1144  static arch_register_req_t const *in_reqs[] = {
1145  &ia32_class_reg_req_gp,
1146  &ia32_class_reg_req_gp,
1147  &arch_memory_requirement,
1148  &ia32_class_reg_req_gp,
1149  &ia32_class_reg_req_gp,
1150  &ia32_class_reg_req_flags,
1151  };
1152 
1153  /* construct in array */
1154  ir_node *const in[] = {
1155  base,
1156  index,
1157  mem,
1158  val_false,
1159  val_true,
1160  eflags,
1161  };
1162 
1163  ir_graph *const irg = get_irn_irg(block);
1164  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_CMovcc, ia32_mode_gp, 6, in);
1165 
1166  /* init node attributes */
1167 
1168  /* flags */
1169  arch_irn_flags_t irn_flags = arch_irn_flags_none;
1170  int const n_res = 3;
1171  be_info_init_irn(res, irn_flags, in_reqs, n_res);
1172  ia32_condcode_attr_t *const attr = (ia32_condcode_attr_t*)get_irn_generic_attr(res);
1173  (void)attr; /* avoid potential warning */
1174  init_ia32_attributes(res, size);
1175  init_ia32_condcode_attributes(res, condition_code);
1176  set_ia32_am_support(res, ia32_am_binary);
1177  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
1178  out_infos[0].req = &ia32_requirements_gp_in_r3_in_r4;
1179  out_infos[1].req = &arch_no_requirement;
1180  out_infos[2].req = &arch_memory_requirement;
1181 
1182  verify_new_node(res);
1183  return optimize_node(res);
1184 }
1185 
1186 ir_node *new_bd_ia32_Call(dbg_info *dbgi, ir_node *block, int const arity, ir_node *const *const in, arch_register_req_t const **const in_reqs, int n_res, uint8_t pop, uint8_t n_reg_results)
1187 {
1188 
1189 
1190  ir_graph *const irg = get_irn_irg(block);
1191  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Call, mode_T, arity, in);
1192 
1193  /* init node attributes */
1194 
1195  /* flags */
1196  arch_irn_flags_t irn_flags = arch_irn_flags_none;
1197  irn_flags |= arch_irn_flag_modify_flags;
1198  be_info_init_irn(res, irn_flags, in_reqs, n_res);
1199  ia32_call_attr_t *const attr = (ia32_call_attr_t*)get_irn_generic_attr(res);
1200  (void)attr; /* avoid potential warning */
1201  x86_insn_size_t const size = X86_SIZE_32;
1202  init_ia32_attributes(res, size);
1203  init_ia32_call_attributes(res, pop, n_reg_results);
1204  set_ia32_am_support(res, ia32_am_unary);
1205 
1206  verify_new_node(res);
1207  return optimize_node(res);
1208 }
1209 
1210 ir_node *new_bd_ia32_ChangeCW(dbg_info *dbgi, ir_node *block)
1211 {
1212  arch_register_req_t const **const in_reqs = NULL;
1213 
1214 
1215  ir_graph *const irg = get_irn_irg(block);
1216  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_ChangeCW, ia32_mode_fpcw, 0, NULL);
1217 
1218  /* init node attributes */
1219 
1220  /* flags */
1221  arch_irn_flags_t irn_flags = arch_irn_flags_none;
1222  irn_flags |= arch_irn_flag_not_scheduled;
1223  int const n_res = 1;
1224  be_info_init_irn(res, irn_flags, in_reqs, n_res);
1225  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
1226  (void)attr; /* avoid potential warning */
1227  x86_insn_size_t const size = X86_SIZE_32;
1228  init_ia32_attributes(res, size);
1229  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
1230  out_infos[0].req = &ia32_class_reg_req_fpcw;
1231 
1232  verify_new_node(res);
1233  return optimize_node(res);
1234 }
1235 
1236 ir_node *new_bd_ia32_Cltd(dbg_info *dbgi, ir_node *block, ir_node *val)
1237 {
1238  static arch_register_req_t const *in_reqs[] = {
1239  &ia32_single_reg_req_gp_eax,
1240  };
1241 
1242  /* construct in array */
1243  ir_node *const in[] = {
1244  val,
1245  };
1246 
1247  ir_graph *const irg = get_irn_irg(block);
1248  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Cltd, ia32_mode_gp, 1, in);
1249 
1250  /* init node attributes */
1251 
1252  /* flags */
1253  arch_irn_flags_t irn_flags = arch_irn_flags_none;
1254  int const n_res = 1;
1255  be_info_init_irn(res, irn_flags, in_reqs, n_res);
1256  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
1257  (void)attr; /* avoid potential warning */
1258  x86_insn_size_t const size = X86_SIZE_32;
1259  init_ia32_attributes(res, size);
1260  arch_set_additional_pressure(res, &ia32_reg_classes[CLASS_ia32_gp], 1);
1261  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
1262  out_infos[0].req = &ia32_single_reg_req_gp_edx;
1263 
1264  verify_new_node(res);
1265  return optimize_node(res);
1266 }
1267 
1268 ir_node *new_bd_ia32_Cmc(dbg_info *dbgi, ir_node *block, ir_node *op0)
1269 {
1270  static arch_register_req_t const *in_reqs[] = {
1271  &ia32_class_reg_req_flags,
1272  };
1273 
1274  /* construct in array */
1275  ir_node *const in[] = {
1276  op0,
1277  };
1278 
1279  ir_graph *const irg = get_irn_irg(block);
1280  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Cmc, ia32_mode_flags, 1, in);
1281 
1282  /* init node attributes */
1283 
1284  /* flags */
1285  arch_irn_flags_t irn_flags = arch_irn_flags_none;
1286  irn_flags |= arch_irn_flag_modify_flags;
1287  int const n_res = 1;
1288  be_info_init_irn(res, irn_flags, in_reqs, n_res);
1289  ia32_condcode_attr_t *const attr = (ia32_condcode_attr_t*)get_irn_generic_attr(res);
1290  (void)attr; /* avoid potential warning */
1291  x86_condition_code_t condition_code = x86_cc_carry;
1292  x86_insn_size_t const size = X86_SIZE_32;
1293  init_ia32_attributes(res, size);
1294  init_ia32_condcode_attributes(res, condition_code);
1295  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
1296  out_infos[0].req = &ia32_class_reg_req_flags;
1297 
1298  verify_new_node(res);
1299  return optimize_node(res);
1300 }
1301 
1302 ir_node *new_bd_ia32_Cmp(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size, bool ins_permuted)
1303 {
1304  static arch_register_req_t const *in_reqs[] = {
1305  &ia32_class_reg_req_gp,
1306  &ia32_class_reg_req_gp,
1307  &arch_memory_requirement,
1308  &ia32_class_reg_req_gp,
1309  &ia32_class_reg_req_gp,
1310  };
1311 
1312  /* construct in array */
1313  ir_node *const in[] = {
1314  base,
1315  index,
1316  mem,
1317  left,
1318  right,
1319  };
1320 
1321  ir_graph *const irg = get_irn_irg(block);
1322  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Cmp, ia32_mode_flags, 5, in);
1323 
1324  /* init node attributes */
1325 
1326  /* flags */
1327  arch_irn_flags_t irn_flags = arch_irn_flags_none;
1328  irn_flags |= arch_irn_flag_modify_flags;
1329  irn_flags |= arch_irn_flag_rematerializable;
1330  int const n_res = 3;
1331  be_info_init_irn(res, irn_flags, in_reqs, n_res);
1332  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
1333  (void)attr; /* avoid potential warning */
1334  init_ia32_attributes(res, size);
1335  set_ia32_am_support(res, ia32_am_binary);
1336  attr->ins_permuted = ins_permuted;
1337  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
1338  out_infos[0].req = &ia32_class_reg_req_flags;
1339  out_infos[1].req = &arch_no_requirement;
1340  out_infos[2].req = &arch_memory_requirement;
1341 
1342  verify_new_node(res);
1343  return optimize_node(res);
1344 }
1345 
1346 ir_node *new_bd_ia32_Cmp_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size, bool ins_permuted)
1347 {
1348  static arch_register_req_t const *in_reqs[] = {
1349  &ia32_class_reg_req_gp,
1350  &ia32_class_reg_req_gp,
1351  &arch_memory_requirement,
1352  &ia32_requirements_gp_eax_ebx_ecx_edx,
1353  &ia32_requirements_gp_eax_ebx_ecx_edx,
1354  };
1355 
1356  /* construct in array */
1357  ir_node *const in[] = {
1358  base,
1359  index,
1360  mem,
1361  left,
1362  right,
1363  };
1364 
1365  ir_graph *const irg = get_irn_irg(block);
1366  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Cmp, ia32_mode_flags, 5, in);
1367 
1368  /* init node attributes */
1369 
1370  /* flags */
1371  arch_irn_flags_t irn_flags = arch_irn_flags_none;
1372  irn_flags |= arch_irn_flag_modify_flags;
1373  irn_flags |= arch_irn_flag_rematerializable;
1374  int const n_res = 3;
1375  be_info_init_irn(res, irn_flags, in_reqs, n_res);
1376  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
1377  (void)attr; /* avoid potential warning */
1378  init_ia32_attributes(res, size);
1379  set_ia32_am_support(res, ia32_am_binary);
1380  attr->ins_permuted = ins_permuted;
1381  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
1382  out_infos[0].req = &ia32_class_reg_req_flags;
1383  out_infos[1].req = &arch_no_requirement;
1384  out_infos[2].req = &arch_memory_requirement;
1385 
1386  verify_new_node(res);
1387  return optimize_node(res);
1388 }
1389 
1390 ir_node *new_bd_ia32_CmpXChgMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *old, ir_node *new, x86_insn_size_t size)
1391 {
1392  static arch_register_req_t const *in_reqs[] = {
1393  &ia32_class_reg_req_gp,
1394  &ia32_class_reg_req_gp,
1395  &arch_memory_requirement,
1396  &ia32_single_reg_req_gp_eax,
1397  &ia32_class_reg_req_gp,
1398  };
1399 
1400  /* construct in array */
1401  ir_node *const in[] = {
1402  base,
1403  index,
1404  mem,
1405  old,
1406  new,
1407  };
1408 
1409  ir_graph *const irg = get_irn_irg(block);
1410  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_CmpXChgMem, mode_T, 5, in);
1411 
1412  /* init node attributes */
1413 
1414  /* flags */
1415  arch_irn_flags_t irn_flags = arch_irn_flags_none;
1416  irn_flags |= arch_irn_flag_modify_flags;
1417  irn_flags |= arch_irn_flag_rematerializable;
1418  int const n_res = 3;
1419  be_info_init_irn(res, irn_flags, in_reqs, n_res);
1420  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
1421  (void)attr; /* avoid potential warning */
1422  init_ia32_attributes(res, size);
1423  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
1424  out_infos[0].req = &ia32_single_reg_req_gp_eax;
1425  out_infos[1].req = &ia32_class_reg_req_flags;
1426  out_infos[2].req = &arch_memory_requirement;
1427 
1428  verify_new_node(res);
1429  return optimize_node(res);
1430 }
1431 
1432 ir_node *new_bd_ia32_Const(dbg_info *dbgi, ir_node *block, const x86_imm32_t *imm)
1433 {
1434  arch_register_req_t const **const in_reqs = NULL;
1435 
1436 
1437  ir_graph *const irg = get_irn_irg(block);
1438  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Const, ia32_mode_gp, 0, NULL);
1439 
1440  /* init node attributes */
1441 
1442  /* flags */
1443  arch_irn_flags_t irn_flags = arch_irn_flags_none;
1444  irn_flags |= arch_irn_flag_rematerializable;
1445  int const n_res = 1;
1446  be_info_init_irn(res, irn_flags, in_reqs, n_res);
1447  ia32_immediate_attr_t *const attr = (ia32_immediate_attr_t*)get_irn_generic_attr(res);
1448  (void)attr; /* avoid potential warning */
1449  x86_insn_size_t const size = X86_SIZE_32;
1450  init_ia32_attributes(res, size);
1451  init_ia32_immediate_attributes(res, imm);
1452  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
1453  out_infos[0].req = &ia32_class_reg_req_gp;
1454 
1455  verify_new_node(res);
1456  return optimize_node(res);
1457 }
1458 
1459 ir_node *new_bd_ia32_Conv_FP2FP(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size)
1460 {
1461  static arch_register_req_t const *in_reqs[] = {
1462  &ia32_class_reg_req_gp,
1463  &ia32_class_reg_req_gp,
1464  &arch_memory_requirement,
1465  &ia32_class_reg_req_xmm,
1466  };
1467 
1468  /* construct in array */
1469  ir_node *const in[] = {
1470  base,
1471  index,
1472  mem,
1473  val,
1474  };
1475 
1476  ir_graph *const irg = get_irn_irg(block);
1477  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Conv_FP2FP, ia32_mode_float64, 4, in);
1478 
1479  /* init node attributes */
1480 
1481  /* flags */
1482  arch_irn_flags_t irn_flags = arch_irn_flags_none;
1483  int const n_res = 2;
1484  be_info_init_irn(res, irn_flags, in_reqs, n_res);
1485  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
1486  (void)attr; /* avoid potential warning */
1487  init_ia32_attributes(res, size);
1488  set_ia32_am_support(res, ia32_am_unary);
1489  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
1490  out_infos[0].req = &ia32_class_reg_req_xmm;
1491  out_infos[1].req = &arch_memory_requirement;
1492 
1493  verify_new_node(res);
1494  return optimize_node(res);
1495 }
1496 
1497 ir_node *new_bd_ia32_Conv_FP2I(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size)
1498 {
1499  static arch_register_req_t const *in_reqs[] = {
1500  &ia32_class_reg_req_gp,
1501  &ia32_class_reg_req_gp,
1502  &arch_memory_requirement,
1503  &ia32_class_reg_req_xmm,
1504  };
1505 
1506  /* construct in array */
1507  ir_node *const in[] = {
1508  base,
1509  index,
1510  mem,
1511  val,
1512  };
1513 
1514  ir_graph *const irg = get_irn_irg(block);
1515  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Conv_FP2I, ia32_mode_gp, 4, in);
1516 
1517  /* init node attributes */
1518 
1519  /* flags */
1520  arch_irn_flags_t irn_flags = arch_irn_flags_none;
1521  int const n_res = 2;
1522  be_info_init_irn(res, irn_flags, in_reqs, n_res);
1523  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
1524  (void)attr; /* avoid potential warning */
1525  init_ia32_attributes(res, size);
1526  set_ia32_am_support(res, ia32_am_unary);
1527  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
1528  out_infos[0].req = &ia32_class_reg_req_gp;
1529  out_infos[1].req = &arch_memory_requirement;
1530 
1531  verify_new_node(res);
1532  return optimize_node(res);
1533 }
1534 
1535 ir_node *new_bd_ia32_Conv_I2FP(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size)
1536 {
1537  static arch_register_req_t const *in_reqs[] = {
1538  &ia32_class_reg_req_gp,
1539  &ia32_class_reg_req_gp,
1540  &arch_memory_requirement,
1541  &ia32_class_reg_req_gp,
1542  };
1543 
1544  /* construct in array */
1545  ir_node *const in[] = {
1546  base,
1547  index,
1548  mem,
1549  val,
1550  };
1551 
1552  ir_graph *const irg = get_irn_irg(block);
1553  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Conv_I2FP, ia32_mode_float64, 4, in);
1554 
1555  /* init node attributes */
1556 
1557  /* flags */
1558  arch_irn_flags_t irn_flags = arch_irn_flags_none;
1559  int const n_res = 2;
1560  be_info_init_irn(res, irn_flags, in_reqs, n_res);
1561  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
1562  (void)attr; /* avoid potential warning */
1563  init_ia32_attributes(res, size);
1564  set_ia32_am_support(res, ia32_am_unary);
1565  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
1566  out_infos[0].req = &ia32_class_reg_req_xmm;
1567  out_infos[1].req = &arch_memory_requirement;
1568 
1569  verify_new_node(res);
1570  return optimize_node(res);
1571 }
1572 
1573 ir_node *new_bd_ia32_Conv_I2I(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size, bool sign_extend)
1574 {
1575  static arch_register_req_t const *in_reqs[] = {
1576  &ia32_class_reg_req_gp,
1577  &ia32_class_reg_req_gp,
1578  &arch_memory_requirement,
1579  &ia32_class_reg_req_gp,
1580  };
1581 
1582  /* construct in array */
1583  ir_node *const in[] = {
1584  base,
1585  index,
1586  mem,
1587  val,
1588  };
1589 
1590  ir_graph *const irg = get_irn_irg(block);
1591  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Conv_I2I, ia32_mode_gp, 4, in);
1592 
1593  /* init node attributes */
1594 
1595  /* flags */
1596  arch_irn_flags_t irn_flags = arch_irn_flags_none;
1597  int const n_res = 5;
1598  be_info_init_irn(res, irn_flags, in_reqs, n_res);
1599  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
1600  (void)attr; /* avoid potential warning */
1601  init_ia32_attributes(res, size);
1602  set_ia32_am_support(res, ia32_am_unary);
1603  attr->sign_extend = sign_extend;
1604  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
1605  out_infos[0].req = &ia32_class_reg_req_gp;
1606  out_infos[1].req = &arch_no_requirement;
1607  out_infos[2].req = &arch_memory_requirement;
1608  out_infos[3].req = &arch_exec_requirement;
1609  out_infos[4].req = &arch_exec_requirement;
1610 
1611  verify_new_node(res);
1612  return optimize_node(res);
1613 }
1614 
1615 ir_node *new_bd_ia32_Conv_I2I_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size, bool sign_extend)
1616 {
1617  static arch_register_req_t const *in_reqs[] = {
1618  &ia32_class_reg_req_gp,
1619  &ia32_class_reg_req_gp,
1620  &arch_memory_requirement,
1621  &ia32_requirements_gp_eax_ebx_ecx_edx,
1622  };
1623 
1624  /* construct in array */
1625  ir_node *const in[] = {
1626  base,
1627  index,
1628  mem,
1629  val,
1630  };
1631 
1632  ir_graph *const irg = get_irn_irg(block);
1633  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Conv_I2I, ia32_mode_gp, 4, in);
1634 
1635  /* init node attributes */
1636 
1637  /* flags */
1638  arch_irn_flags_t irn_flags = arch_irn_flags_none;
1639  int const n_res = 5;
1640  be_info_init_irn(res, irn_flags, in_reqs, n_res);
1641  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
1642  (void)attr; /* avoid potential warning */
1643  init_ia32_attributes(res, size);
1644  set_ia32_am_support(res, ia32_am_unary);
1645  attr->sign_extend = sign_extend;
1646  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
1647  out_infos[0].req = &ia32_class_reg_req_gp;
1648  out_infos[1].req = &arch_no_requirement;
1649  out_infos[2].req = &arch_memory_requirement;
1650  out_infos[3].req = &arch_exec_requirement;
1651  out_infos[4].req = &arch_exec_requirement;
1652 
1653  verify_new_node(res);
1654  return optimize_node(res);
1655 }
1656 
1657 ir_node *new_bd_ia32_CopyB(dbg_info *dbgi, ir_node *block, ir_node *dest, ir_node *source, ir_node *count, ir_node *mem, unsigned size)
1658 {
1659  static arch_register_req_t const *in_reqs[] = {
1660  &ia32_single_reg_req_gp_edi,
1661  &ia32_single_reg_req_gp_esi,
1662  &ia32_single_reg_req_gp_ecx,
1663  &arch_memory_requirement,
1664  };
1665 
1666  /* construct in array */
1667  ir_node *const in[] = {
1668  dest,
1669  source,
1670  count,
1671  mem,
1672  };
1673 
1674  ir_graph *const irg = get_irn_irg(block);
1675  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_CopyB, mode_T, 4, in);
1676 
1677  /* init node attributes */
1678 
1679  /* flags */
1680  arch_irn_flags_t irn_flags = arch_irn_flags_none;
1681  int const n_res = 4;
1682  be_info_init_irn(res, irn_flags, in_reqs, n_res);
1683  ia32_copyb_attr_t *const attr = (ia32_copyb_attr_t*)get_irn_generic_attr(res);
1684  (void)attr; /* avoid potential warning */
1685  init_ia32_attributes(res, size);
1686  init_ia32_copyb_attributes(res, size);
1687  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
1688  out_infos[0].req = &ia32_single_reg_req_gp_edi;
1689  out_infos[1].req = &ia32_single_reg_req_gp_esi;
1690  out_infos[2].req = &ia32_single_reg_req_gp_ecx;
1691  out_infos[3].req = &arch_memory_requirement;
1692 
1693  verify_new_node(res);
1694  return optimize_node(res);
1695 }
1696 
1697 ir_node *new_bd_ia32_CopyB_i(dbg_info *dbgi, ir_node *block, ir_node *dest, ir_node *source, ir_node *mem, unsigned size)
1698 {
1699  static arch_register_req_t const *in_reqs[] = {
1700  &ia32_single_reg_req_gp_edi,
1701  &ia32_single_reg_req_gp_esi,
1702  &arch_memory_requirement,
1703  };
1704 
1705  /* construct in array */
1706  ir_node *const in[] = {
1707  dest,
1708  source,
1709  mem,
1710  };
1711 
1712  ir_graph *const irg = get_irn_irg(block);
1713  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_CopyB_i, mode_T, 3, in);
1714 
1715  /* init node attributes */
1716 
1717  /* flags */
1718  arch_irn_flags_t irn_flags = arch_irn_flags_none;
1719  int const n_res = 3;
1720  be_info_init_irn(res, irn_flags, in_reqs, n_res);
1721  ia32_copyb_attr_t *const attr = (ia32_copyb_attr_t*)get_irn_generic_attr(res);
1722  (void)attr; /* avoid potential warning */
1723  init_ia32_attributes(res, size);
1724  init_ia32_copyb_attributes(res, size);
1725  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
1726  out_infos[0].req = &ia32_single_reg_req_gp_edi;
1727  out_infos[1].req = &ia32_single_reg_req_gp_esi;
1728  out_infos[2].req = &arch_memory_requirement;
1729 
1730  verify_new_node(res);
1731  return optimize_node(res);
1732 }
1733 
1734 ir_node *new_bd_ia32_CopyEbpEsp(dbg_info *dbgi, ir_node *block, ir_node *ebp)
1735 {
1736  static arch_register_req_t const *in_reqs[] = {
1737  &ia32_single_reg_req_gp_ebp,
1738  };
1739 
1740  /* construct in array */
1741  ir_node *const in[] = {
1742  ebp,
1743  };
1744 
1745  ir_graph *const irg = get_irn_irg(block);
1746  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_CopyEbpEsp, ia32_mode_gp, 1, in);
1747 
1748  /* init node attributes */
1749 
1750  /* flags */
1751  arch_irn_flags_t irn_flags = arch_irn_flags_none;
1752  int const n_res = 1;
1753  be_info_init_irn(res, irn_flags, in_reqs, n_res);
1754  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
1755  (void)attr; /* avoid potential warning */
1756  x86_insn_size_t const size = X86_SIZE_32;
1757  init_ia32_attributes(res, size);
1758  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
1759  out_infos[0].req = &ia32_requirements_gp_esp_I;
1760 
1761  verify_new_node(res);
1762  return optimize_node(res);
1763 }
1764 
1765 ir_node *new_bd_ia32_CvtSI2SD(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size)
1766 {
1767  static arch_register_req_t const *in_reqs[] = {
1768  &ia32_class_reg_req_gp,
1769  &ia32_class_reg_req_gp,
1770  &arch_memory_requirement,
1771  &ia32_class_reg_req_gp,
1772  };
1773 
1774  /* construct in array */
1775  ir_node *const in[] = {
1776  base,
1777  index,
1778  mem,
1779  val,
1780  };
1781 
1782  ir_graph *const irg = get_irn_irg(block);
1783  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_CvtSI2SD, ia32_mode_float64, 4, in);
1784 
1785  /* init node attributes */
1786 
1787  /* flags */
1788  arch_irn_flags_t irn_flags = arch_irn_flags_none;
1789  int const n_res = 1;
1790  be_info_init_irn(res, irn_flags, in_reqs, n_res);
1791  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
1792  (void)attr; /* avoid potential warning */
1793  init_ia32_attributes(res, size);
1794  set_ia32_am_support(res, ia32_am_unary);
1795  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
1796  out_infos[0].req = &ia32_class_reg_req_xmm;
1797 
1798  verify_new_node(res);
1799  return optimize_node(res);
1800 }
1801 
1802 ir_node *new_bd_ia32_CvtSI2SS(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size)
1803 {
1804  static arch_register_req_t const *in_reqs[] = {
1805  &ia32_class_reg_req_gp,
1806  &ia32_class_reg_req_gp,
1807  &arch_memory_requirement,
1808  &ia32_class_reg_req_gp,
1809  };
1810 
1811  /* construct in array */
1812  ir_node *const in[] = {
1813  base,
1814  index,
1815  mem,
1816  val,
1817  };
1818 
1819  ir_graph *const irg = get_irn_irg(block);
1820  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_CvtSI2SS, ia32_mode_float64, 4, in);
1821 
1822  /* init node attributes */
1823 
1824  /* flags */
1825  arch_irn_flags_t irn_flags = arch_irn_flags_none;
1826  int const n_res = 1;
1827  be_info_init_irn(res, irn_flags, in_reqs, n_res);
1828  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
1829  (void)attr; /* avoid potential warning */
1830  init_ia32_attributes(res, size);
1831  set_ia32_am_support(res, ia32_am_unary);
1832  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
1833  out_infos[0].req = &ia32_class_reg_req_xmm;
1834 
1835  verify_new_node(res);
1836  return optimize_node(res);
1837 }
1838 
1839 ir_node *new_bd_ia32_Cwtl(dbg_info *dbgi, ir_node *block, ir_node *val)
1840 {
1841  static arch_register_req_t const *in_reqs[] = {
1842  &ia32_single_reg_req_gp_eax,
1843  };
1844 
1845  /* construct in array */
1846  ir_node *const in[] = {
1847  val,
1848  };
1849 
1850  ir_graph *const irg = get_irn_irg(block);
1851  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Cwtl, ia32_mode_gp, 1, in);
1852 
1853  /* init node attributes */
1854 
1855  /* flags */
1856  arch_irn_flags_t irn_flags = arch_irn_flags_none;
1857  int const n_res = 1;
1858  be_info_init_irn(res, irn_flags, in_reqs, n_res);
1859  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
1860  (void)attr; /* avoid potential warning */
1861  x86_insn_size_t const size = X86_SIZE_32;
1862  init_ia32_attributes(res, size);
1863  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
1864  out_infos[0].req = &ia32_single_reg_req_gp_eax;
1865 
1866  verify_new_node(res);
1867  return optimize_node(res);
1868 }
1869 
1870 ir_node *new_bd_ia32_Dec(dbg_info *dbgi, ir_node *block, ir_node *val, x86_insn_size_t size)
1871 {
1872  static arch_register_req_t const *in_reqs[] = {
1873  &ia32_class_reg_req_gp,
1874  };
1875 
1876  /* construct in array */
1877  ir_node *const in[] = {
1878  val,
1879  };
1880 
1881  ir_graph *const irg = get_irn_irg(block);
1882  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Dec, ia32_mode_gp, 1, in);
1883 
1884  /* init node attributes */
1885 
1886  /* flags */
1887  arch_irn_flags_t irn_flags = arch_irn_flags_none;
1888  irn_flags |= arch_irn_flag_modify_flags;
1889  irn_flags |= arch_irn_flag_rematerializable;
1890  int const n_res = 2;
1891  be_info_init_irn(res, irn_flags, in_reqs, n_res);
1892  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
1893  (void)attr; /* avoid potential warning */
1894  init_ia32_attributes(res, size);
1895  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
1896  out_infos[0].req = &ia32_requirements_gp_in_r0;
1897  out_infos[1].req = &ia32_class_reg_req_flags;
1898 
1899  verify_new_node(res);
1900  return optimize_node(res);
1901 }
1902 
1903 ir_node *new_bd_ia32_DecMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, x86_insn_size_t size)
1904 {
1905  static arch_register_req_t const *in_reqs[] = {
1906  &ia32_class_reg_req_gp,
1907  &ia32_class_reg_req_gp,
1908  &arch_memory_requirement,
1909  };
1910 
1911  /* construct in array */
1912  ir_node *const in[] = {
1913  base,
1914  index,
1915  mem,
1916  };
1917 
1918  ir_graph *const irg = get_irn_irg(block);
1919  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_DecMem, mode_T, 3, in);
1920 
1921  /* init node attributes */
1922 
1923  /* flags */
1924  arch_irn_flags_t irn_flags = arch_irn_flags_none;
1925  irn_flags |= arch_irn_flag_modify_flags;
1926  irn_flags |= arch_irn_flag_rematerializable;
1927  int const n_res = 3;
1928  be_info_init_irn(res, irn_flags, in_reqs, n_res);
1929  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
1930  (void)attr; /* avoid potential warning */
1931  init_ia32_attributes(res, size);
1932  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
1933  out_infos[0].req = &arch_no_requirement;
1934  out_infos[1].req = &ia32_class_reg_req_flags;
1935  out_infos[2].req = &arch_memory_requirement;
1936 
1937  verify_new_node(res);
1938  return optimize_node(res);
1939 }
1940 
1941 ir_node *new_bd_ia32_Div(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *divisor, ir_node *dividend_low, ir_node *dividend_high, x86_insn_size_t size)
1942 {
1943  static arch_register_req_t const *in_reqs[] = {
1944  &ia32_class_reg_req_gp,
1945  &ia32_class_reg_req_gp,
1946  &arch_memory_requirement,
1947  &ia32_class_reg_req_gp,
1948  &ia32_single_reg_req_gp_eax,
1949  &ia32_single_reg_req_gp_edx,
1950  };
1951 
1952  /* construct in array */
1953  ir_node *const in[] = {
1954  base,
1955  index,
1956  mem,
1957  divisor,
1958  dividend_low,
1959  dividend_high,
1960  };
1961 
1962  ir_graph *const irg = get_irn_irg(block);
1963  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Div, mode_T, 6, in);
1964 
1965  /* init node attributes */
1966 
1967  /* flags */
1968  arch_irn_flags_t irn_flags = arch_irn_flags_none;
1969  irn_flags |= arch_irn_flag_modify_flags;
1970  int const n_res = 6;
1971  be_info_init_irn(res, irn_flags, in_reqs, n_res);
1972  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
1973  (void)attr; /* avoid potential warning */
1974  init_ia32_attributes(res, size);
1975  set_ia32_am_support(res, ia32_am_unary);
1976  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
1977  out_infos[0].req = &ia32_single_reg_req_gp_eax;
1978  out_infos[1].req = &ia32_class_reg_req_flags;
1979  out_infos[2].req = &arch_memory_requirement;
1980  out_infos[3].req = &ia32_single_reg_req_gp_edx;
1981  out_infos[4].req = &arch_exec_requirement;
1982  out_infos[5].req = &arch_exec_requirement;
1983 
1984  verify_new_node(res);
1985  return optimize_node(res);
1986 }
1987 
1988 ir_node *new_bd_ia32_Divs(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size)
1989 {
1990  static arch_register_req_t const *in_reqs[] = {
1991  &ia32_class_reg_req_gp,
1992  &ia32_class_reg_req_gp,
1993  &arch_memory_requirement,
1994  &ia32_class_reg_req_xmm,
1995  &ia32_class_reg_req_xmm,
1996  };
1997 
1998  /* construct in array */
1999  ir_node *const in[] = {
2000  base,
2001  index,
2002  mem,
2003  left,
2004  right,
2005  };
2006 
2007  ir_graph *const irg = get_irn_irg(block);
2008  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Divs, mode_T, 5, in);
2009 
2010  /* init node attributes */
2011 
2012  /* flags */
2013  arch_irn_flags_t irn_flags = arch_irn_flags_none;
2014  irn_flags |= arch_irn_flag_rematerializable;
2015  int const n_res = 3;
2016  be_info_init_irn(res, irn_flags, in_reqs, n_res);
2017  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
2018  (void)attr; /* avoid potential warning */
2019  init_ia32_attributes(res, size);
2020  set_ia32_am_support(res, ia32_am_binary);
2021  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
2022  out_infos[0].req = &ia32_requirements_xmm_in_r3_not_in_r4;
2023  out_infos[1].req = &ia32_class_reg_req_flags;
2024  out_infos[2].req = &arch_memory_requirement;
2025 
2026  verify_new_node(res);
2027  return optimize_node(res);
2028 }
2029 
2030 ir_node *new_bd_ia32_Enter(dbg_info *dbgi, ir_node *block, ir_node *op0)
2031 {
2032  static arch_register_req_t const *in_reqs[] = {
2033  &ia32_single_reg_req_gp_esp,
2034  };
2035 
2036  /* construct in array */
2037  ir_node *const in[] = {
2038  op0,
2039  };
2040 
2041  ir_graph *const irg = get_irn_irg(block);
2042  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Enter, mode_T, 1, in);
2043 
2044  /* init node attributes */
2045 
2046  /* flags */
2047  arch_irn_flags_t irn_flags = arch_irn_flags_none;
2048  int const n_res = 3;
2049  be_info_init_irn(res, irn_flags, in_reqs, n_res);
2050  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
2051  (void)attr; /* avoid potential warning */
2052  x86_insn_size_t const size = X86_SIZE_32;
2053  init_ia32_attributes(res, size);
2054  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
2055  out_infos[0].req = &ia32_single_reg_req_gp_ebp;
2056  out_infos[1].req = &ia32_requirements_gp_esp_I;
2057  out_infos[2].req = &arch_memory_requirement;
2058 
2059  verify_new_node(res);
2060  return optimize_node(res);
2061 }
2062 
2063 ir_node *new_bd_ia32_FldCW(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem)
2064 {
2065  static arch_register_req_t const *in_reqs[] = {
2066  &ia32_class_reg_req_gp,
2067  &ia32_class_reg_req_gp,
2068  &arch_memory_requirement,
2069  };
2070 
2071  /* construct in array */
2072  ir_node *const in[] = {
2073  base,
2074  index,
2075  mem,
2076  };
2077 
2078  ir_graph *const irg = get_irn_irg(block);
2079  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_FldCW, ia32_mode_fpcw, 3, in);
2080 
2081  /* init node attributes */
2082 
2083  /* flags */
2084  arch_irn_flags_t irn_flags = arch_irn_flags_none;
2085  int const n_res = 1;
2086  be_info_init_irn(res, irn_flags, in_reqs, n_res);
2087  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
2088  (void)attr; /* avoid potential warning */
2089  x86_insn_size_t const size = X86_SIZE_16;
2090  init_ia32_attributes(res, size);
2091  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
2092  out_infos[0].req = &ia32_class_reg_req_fpcw;
2093 
2094  verify_new_node(res);
2095  return optimize_node(res);
2096 }
2097 
2098 ir_node *new_bd_ia32_FnstCW(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *fpcw)
2099 {
2100  static arch_register_req_t const *in_reqs[] = {
2101  &ia32_class_reg_req_gp,
2102  &ia32_class_reg_req_gp,
2103  &arch_memory_requirement,
2104  &ia32_class_reg_req_fpcw,
2105  };
2106 
2107  /* construct in array */
2108  ir_node *const in[] = {
2109  base,
2110  index,
2111  mem,
2112  fpcw,
2113  };
2114 
2115  ir_graph *const irg = get_irn_irg(block);
2116  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_FnstCW, mode_M, 4, in);
2117 
2118  /* init node attributes */
2119 
2120  /* flags */
2121  arch_irn_flags_t irn_flags = arch_irn_flags_none;
2122  int const n_res = 1;
2123  be_info_init_irn(res, irn_flags, in_reqs, n_res);
2124  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
2125  (void)attr; /* avoid potential warning */
2126  x86_insn_size_t const size = X86_SIZE_16;
2127  init_ia32_attributes(res, size);
2128  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
2129  out_infos[0].req = &arch_memory_requirement;
2130 
2131  verify_new_node(res);
2132  return optimize_node(res);
2133 }
2134 
2135 ir_node *new_bd_ia32_FnstCWNOP(dbg_info *dbgi, ir_node *block, ir_node *fpcw)
2136 {
2137  static arch_register_req_t const *in_reqs[] = {
2138  &ia32_class_reg_req_fpcw,
2139  };
2140 
2141  /* construct in array */
2142  ir_node *const in[] = {
2143  fpcw,
2144  };
2145 
2146  ir_graph *const irg = get_irn_irg(block);
2147  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_FnstCWNOP, mode_M, 1, in);
2148 
2149  /* init node attributes */
2150 
2151  /* flags */
2152  arch_irn_flags_t irn_flags = arch_irn_flags_none;
2153  int const n_res = 1;
2154  be_info_init_irn(res, irn_flags, in_reqs, n_res);
2155  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
2156  (void)attr; /* avoid potential warning */
2157  x86_insn_size_t const size = X86_SIZE_16;
2158  init_ia32_attributes(res, size);
2159  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
2160  out_infos[0].req = &arch_memory_requirement;
2161 
2162  verify_new_node(res);
2163  return optimize_node(res);
2164 }
2165 
2166 ir_node *new_bd_ia32_FtstFnstsw(dbg_info *dbgi, ir_node *block, ir_node *left, bool ins_permuted)
2167 {
2168  static arch_register_req_t const *in_reqs[] = {
2169  &ia32_class_reg_req_fp,
2170  };
2171 
2172  /* construct in array */
2173  ir_node *const in[] = {
2174  left,
2175  };
2176 
2177  ir_graph *const irg = get_irn_irg(block);
2178  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_FtstFnstsw, ia32_mode_gp, 1, in);
2179 
2180  /* init node attributes */
2181 
2182  /* flags */
2183  arch_irn_flags_t irn_flags = arch_irn_flags_none;
2184  int const n_res = 1;
2185  be_info_init_irn(res, irn_flags, in_reqs, n_res);
2186  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
2187  (void)attr; /* avoid potential warning */
2188  x86_insn_size_t const size = X86_SIZE_16; ia32_request_x87_sim(irg);
2189  init_ia32_attributes(res, size);
2190  attr->ins_permuted = ins_permuted;
2191  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
2192  out_infos[0].req = &ia32_single_reg_req_gp_eax;
2193 
2194  verify_new_node(res);
2195  return optimize_node(res);
2196 }
2197 
2198 ir_node *new_bd_ia32_FucomFnstsw(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, bool ins_permuted)
2199 {
2200  static arch_register_req_t const *in_reqs[] = {
2201  &ia32_class_reg_req_fp,
2202  &ia32_class_reg_req_fp,
2203  };
2204 
2205  /* construct in array */
2206  ir_node *const in[] = {
2207  left,
2208  right,
2209  };
2210 
2211  ir_graph *const irg = get_irn_irg(block);
2212  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_FucomFnstsw, ia32_mode_gp, 2, in);
2213 
2214  /* init node attributes */
2215 
2216  /* flags */
2217  arch_irn_flags_t irn_flags = arch_irn_flags_none;
2218  int const n_res = 1;
2219  be_info_init_irn(res, irn_flags, in_reqs, n_res);
2220  ia32_x87_attr_t *const attr = (ia32_x87_attr_t*)get_irn_generic_attr(res);
2221  (void)attr; /* avoid potential warning */
2222  x86_insn_size_t const size = X86_SIZE_16;
2223  init_ia32_attributes(res, size);
2224  init_ia32_x87_attributes(res);
2225  attr->attr.ins_permuted = ins_permuted;
2226  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
2227  out_infos[0].req = &ia32_single_reg_req_gp_eax;
2228 
2229  verify_new_node(res);
2230  return optimize_node(res);
2231 }
2232 
2233 ir_node *new_bd_ia32_Fucomi(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, bool ins_permuted)
2234 {
2235  static arch_register_req_t const *in_reqs[] = {
2236  &ia32_class_reg_req_fp,
2237  &ia32_class_reg_req_fp,
2238  };
2239 
2240  /* construct in array */
2241  ir_node *const in[] = {
2242  left,
2243  right,
2244  };
2245 
2246  ir_graph *const irg = get_irn_irg(block);
2247  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Fucomi, ia32_mode_flags, 2, in);
2248 
2249  /* init node attributes */
2250 
2251  /* flags */
2252  arch_irn_flags_t irn_flags = arch_irn_flags_none;
2253  irn_flags |= arch_irn_flag_rematerializable;
2254  int const n_res = 1;
2255  be_info_init_irn(res, irn_flags, in_reqs, n_res);
2256  ia32_x87_attr_t *const attr = (ia32_x87_attr_t*)get_irn_generic_attr(res);
2257  (void)attr; /* avoid potential warning */
2258  x86_insn_size_t const size = X86_SIZE_80;
2259  init_ia32_attributes(res, size);
2260  init_ia32_x87_attributes(res);
2261  attr->attr.ins_permuted = ins_permuted;
2262  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
2263  out_infos[0].req = &ia32_class_reg_req_flags;
2264 
2265  verify_new_node(res);
2266  return optimize_node(res);
2267 }
2268 
2269 ir_node *new_bd_ia32_FucomppFnstsw(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, bool ins_permuted)
2270 {
2271  static arch_register_req_t const *in_reqs[] = {
2272  &ia32_class_reg_req_fp,
2273  &ia32_class_reg_req_fp,
2274  };
2275 
2276  /* construct in array */
2277  ir_node *const in[] = {
2278  left,
2279  right,
2280  };
2281 
2282  ir_graph *const irg = get_irn_irg(block);
2283  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_FucomppFnstsw, ia32_mode_gp, 2, in);
2284 
2285  /* init node attributes */
2286 
2287  /* flags */
2288  arch_irn_flags_t irn_flags = arch_irn_flags_none;
2289  int const n_res = 1;
2290  be_info_init_irn(res, irn_flags, in_reqs, n_res);
2291  ia32_x87_attr_t *const attr = (ia32_x87_attr_t*)get_irn_generic_attr(res);
2292  (void)attr; /* avoid potential warning */
2293  x86_insn_size_t const size = X86_SIZE_16;
2294  init_ia32_attributes(res, size);
2295  init_ia32_x87_attributes(res);
2296  attr->attr.ins_permuted = ins_permuted;
2297  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
2298  out_infos[0].req = &ia32_single_reg_req_gp_eax;
2299 
2300  verify_new_node(res);
2301  return optimize_node(res);
2302 }
2303 
2304 ir_node *new_bd_ia32_GetEIP(dbg_info *dbgi, ir_node *block)
2305 {
2306  arch_register_req_t const **const in_reqs = NULL;
2307 
2308 
2309  ir_graph *const irg = get_irn_irg(block);
2310  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_GetEIP, ia32_mode_gp, 0, NULL);
2311 
2312  /* init node attributes */
2313 
2314  /* flags */
2315  arch_irn_flags_t irn_flags = arch_irn_flags_none;
2316  int const n_res = 1;
2317  be_info_init_irn(res, irn_flags, in_reqs, n_res);
2318  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
2319  (void)attr; /* avoid potential warning */
2320  x86_insn_size_t const size = X86_SIZE_32;
2321  init_ia32_attributes(res, size);
2322  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
2323  out_infos[0].req = &ia32_class_reg_req_gp;
2324 
2325  verify_new_node(res);
2326  return optimize_node(res);
2327 }
2328 
2329 ir_node *new_bd_ia32_IDiv(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *divisor, ir_node *dividend_low, ir_node *dividend_high, x86_insn_size_t size)
2330 {
2331  static arch_register_req_t const *in_reqs[] = {
2332  &ia32_class_reg_req_gp,
2333  &ia32_class_reg_req_gp,
2334  &arch_memory_requirement,
2335  &ia32_class_reg_req_gp,
2336  &ia32_single_reg_req_gp_eax,
2337  &ia32_single_reg_req_gp_edx,
2338  };
2339 
2340  /* construct in array */
2341  ir_node *const in[] = {
2342  base,
2343  index,
2344  mem,
2345  divisor,
2346  dividend_low,
2347  dividend_high,
2348  };
2349 
2350  ir_graph *const irg = get_irn_irg(block);
2351  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_IDiv, mode_T, 6, in);
2352 
2353  /* init node attributes */
2354 
2355  /* flags */
2356  arch_irn_flags_t irn_flags = arch_irn_flags_none;
2357  irn_flags |= arch_irn_flag_modify_flags;
2358  int const n_res = 6;
2359  be_info_init_irn(res, irn_flags, in_reqs, n_res);
2360  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
2361  (void)attr; /* avoid potential warning */
2362  init_ia32_attributes(res, size);
2363  set_ia32_am_support(res, ia32_am_unary);
2364  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
2365  out_infos[0].req = &ia32_single_reg_req_gp_eax;
2366  out_infos[1].req = &ia32_class_reg_req_flags;
2367  out_infos[2].req = &arch_memory_requirement;
2368  out_infos[3].req = &ia32_single_reg_req_gp_edx;
2369  out_infos[4].req = &arch_exec_requirement;
2370  out_infos[5].req = &arch_exec_requirement;
2371 
2372  verify_new_node(res);
2373  return optimize_node(res);
2374 }
2375 
2376 ir_node *new_bd_ia32_IJmp(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *target)
2377 {
2378  static arch_register_req_t const *in_reqs[] = {
2379  &ia32_class_reg_req_gp,
2380  &ia32_class_reg_req_gp,
2381  &arch_memory_requirement,
2382  &ia32_class_reg_req_gp,
2383  };
2384 
2385  /* construct in array */
2386  ir_node *const in[] = {
2387  base,
2388  index,
2389  mem,
2390  target,
2391  };
2392 
2393  ir_graph *const irg = get_irn_irg(block);
2394  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_IJmp, mode_X, 4, in);
2395 
2396  /* init node attributes */
2397 
2398  /* flags */
2399  arch_irn_flags_t irn_flags = arch_irn_flags_none;
2400  int const n_res = 3;
2401  be_info_init_irn(res, irn_flags, in_reqs, n_res);
2402  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
2403  (void)attr; /* avoid potential warning */
2404  x86_insn_size_t const size = X86_SIZE_32;
2405  init_ia32_attributes(res, size);
2406  set_ia32_am_support(res, ia32_am_unary);
2407  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
2408  out_infos[0].req = &arch_exec_requirement;
2409  out_infos[1].req = &arch_no_requirement;
2410  out_infos[2].req = &arch_memory_requirement;
2411 
2412  verify_new_node(res);
2413  return optimize_node(res);
2414 }
2415 
2416 ir_node *new_bd_ia32_IMul(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size)
2417 {
2418  static arch_register_req_t const *in_reqs[] = {
2419  &ia32_class_reg_req_gp,
2420  &ia32_class_reg_req_gp,
2421  &arch_memory_requirement,
2422  &ia32_class_reg_req_gp,
2423  &ia32_class_reg_req_gp,
2424  };
2425 
2426  /* construct in array */
2427  ir_node *const in[] = {
2428  base,
2429  index,
2430  mem,
2431  left,
2432  right,
2433  };
2434 
2435  ir_graph *const irg = get_irn_irg(block);
2436  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_IMul, ia32_mode_gp, 5, in);
2437 
2438  /* init node attributes */
2439 
2440  /* flags */
2441  arch_irn_flags_t irn_flags = arch_irn_flags_none;
2442  irn_flags |= arch_irn_flag_modify_flags;
2443  irn_flags |= arch_irn_flag_rematerializable;
2444  int const n_res = 3;
2445  be_info_init_irn(res, irn_flags, in_reqs, n_res);
2446  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
2447  (void)attr; /* avoid potential warning */
2448  init_ia32_attributes(res, size);
2449  set_ia32_am_support(res, ia32_am_binary);
2450  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
2451  out_infos[0].req = &ia32_requirements_gp_in_r3_in_r4;
2452  out_infos[1].req = &ia32_class_reg_req_flags;
2453  out_infos[2].req = &arch_memory_requirement;
2454 
2455  verify_new_node(res);
2456  return optimize_node(res);
2457 }
2458 
2459 ir_node *new_bd_ia32_IMul_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size)
2460 {
2461  static arch_register_req_t const *in_reqs[] = {
2462  &ia32_class_reg_req_gp,
2463  &ia32_class_reg_req_gp,
2464  &arch_memory_requirement,
2465  &ia32_requirements_gp_eax_ebx_ecx_edx,
2466  &ia32_requirements_gp_eax_ebx_ecx_edx,
2467  };
2468 
2469  /* construct in array */
2470  ir_node *const in[] = {
2471  base,
2472  index,
2473  mem,
2474  left,
2475  right,
2476  };
2477 
2478  ir_graph *const irg = get_irn_irg(block);
2479  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_IMul, ia32_mode_gp, 5, in);
2480 
2481  /* init node attributes */
2482 
2483  /* flags */
2484  arch_irn_flags_t irn_flags = arch_irn_flags_none;
2485  irn_flags |= arch_irn_flag_modify_flags;
2486  irn_flags |= arch_irn_flag_rematerializable;
2487  int const n_res = 3;
2488  be_info_init_irn(res, irn_flags, in_reqs, n_res);
2489  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
2490  (void)attr; /* avoid potential warning */
2491  init_ia32_attributes(res, size);
2492  set_ia32_am_support(res, ia32_am_binary);
2493  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
2494  out_infos[0].req = &ia32_requirements_gp_eax_ebx_ecx_edx_in_r3_in_r4;
2495  out_infos[1].req = &ia32_class_reg_req_flags;
2496  out_infos[2].req = &arch_memory_requirement;
2497 
2498  verify_new_node(res);
2499  return optimize_node(res);
2500 }
2501 
2502 ir_node *new_bd_ia32_IMul1OP(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size)
2503 {
2504  static arch_register_req_t const *in_reqs[] = {
2505  &ia32_class_reg_req_gp,
2506  &ia32_class_reg_req_gp,
2507  &arch_memory_requirement,
2508  &ia32_single_reg_req_gp_eax,
2509  &ia32_class_reg_req_gp,
2510  };
2511 
2512  /* construct in array */
2513  ir_node *const in[] = {
2514  base,
2515  index,
2516  mem,
2517  left,
2518  right,
2519  };
2520 
2521  ir_graph *const irg = get_irn_irg(block);
2522  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_IMul1OP, mode_T, 5, in);
2523 
2524  /* init node attributes */
2525 
2526  /* flags */
2527  arch_irn_flags_t irn_flags = arch_irn_flags_none;
2528  irn_flags |= arch_irn_flag_modify_flags;
2529  int const n_res = 4;
2530  be_info_init_irn(res, irn_flags, in_reqs, n_res);
2531  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
2532  (void)attr; /* avoid potential warning */
2533  init_ia32_attributes(res, size);
2534  set_ia32_am_support(res, ia32_am_binary);
2535  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
2536  out_infos[0].req = &ia32_single_reg_req_gp_eax;
2537  out_infos[1].req = &ia32_class_reg_req_flags;
2538  out_infos[2].req = &arch_memory_requirement;
2539  out_infos[3].req = &ia32_single_reg_req_gp_edx;
2540 
2541  verify_new_node(res);
2542  return optimize_node(res);
2543 }
2544 
2545 ir_node *new_bd_ia32_IMulImm(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size)
2546 {
2547  static arch_register_req_t const *in_reqs[] = {
2548  &ia32_class_reg_req_gp,
2549  &ia32_class_reg_req_gp,
2550  &arch_memory_requirement,
2551  &ia32_class_reg_req_gp,
2552  &ia32_class_reg_req_gp,
2553  };
2554 
2555  /* construct in array */
2556  ir_node *const in[] = {
2557  base,
2558  index,
2559  mem,
2560  left,
2561  right,
2562  };
2563 
2564  ir_graph *const irg = get_irn_irg(block);
2565  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_IMulImm, ia32_mode_gp, 5, in);
2566 
2567  /* init node attributes */
2568 
2569  /* flags */
2570  arch_irn_flags_t irn_flags = arch_irn_flags_none;
2571  irn_flags |= arch_irn_flag_modify_flags;
2572  irn_flags |= arch_irn_flag_rematerializable;
2573  int const n_res = 3;
2574  be_info_init_irn(res, irn_flags, in_reqs, n_res);
2575  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
2576  (void)attr; /* avoid potential warning */
2577  init_ia32_attributes(res, size);
2578  set_ia32_am_support(res, ia32_am_binary);
2579  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
2580  out_infos[0].req = &ia32_class_reg_req_gp;
2581  out_infos[1].req = &ia32_class_reg_req_flags;
2582  out_infos[2].req = &arch_memory_requirement;
2583 
2584  verify_new_node(res);
2585  return optimize_node(res);
2586 }
2587 
2588 ir_node *new_bd_ia32_Immediate(dbg_info *dbgi, ir_node *block, const x86_imm32_t *imm)
2589 {
2590  arch_register_req_t const **const in_reqs = NULL;
2591 
2592 
2593  ir_graph *const irg = get_irn_irg(block);
2594  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Immediate, ia32_mode_gp, 0, NULL);
2595 
2596  /* init node attributes */
2597 
2598  /* flags */
2599  arch_irn_flags_t irn_flags = arch_irn_flags_none;
2600  irn_flags |= arch_irn_flag_not_scheduled;
2601  int const n_res = 1;
2602  be_info_init_irn(res, irn_flags, in_reqs, n_res);
2603  ia32_immediate_attr_t *const attr = (ia32_immediate_attr_t*)get_irn_generic_attr(res);
2604  (void)attr; /* avoid potential warning */
2605  x86_insn_size_t const size = X86_SIZE_32;
2606  init_ia32_attributes(res, size);
2607  init_ia32_immediate_attributes(res, imm);
2608  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
2609  out_infos[0].req = &ia32_requirements_gp_gp_NOREG_I;
2610 
2611  verify_new_node(res);
2612  return optimize_node(res);
2613 }
2614 
2615 ir_node *new_bd_ia32_Inc(dbg_info *dbgi, ir_node *block, ir_node *val, x86_insn_size_t size)
2616 {
2617  static arch_register_req_t const *in_reqs[] = {
2618  &ia32_class_reg_req_gp,
2619  };
2620 
2621  /* construct in array */
2622  ir_node *const in[] = {
2623  val,
2624  };
2625 
2626  ir_graph *const irg = get_irn_irg(block);
2627  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Inc, ia32_mode_gp, 1, in);
2628 
2629  /* init node attributes */
2630 
2631  /* flags */
2632  arch_irn_flags_t irn_flags = arch_irn_flags_none;
2633  irn_flags |= arch_irn_flag_modify_flags;
2634  irn_flags |= arch_irn_flag_rematerializable;
2635  int const n_res = 2;
2636  be_info_init_irn(res, irn_flags, in_reqs, n_res);
2637  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
2638  (void)attr; /* avoid potential warning */
2639  init_ia32_attributes(res, size);
2640  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
2641  out_infos[0].req = &ia32_requirements_gp_in_r0;
2642  out_infos[1].req = &ia32_class_reg_req_flags;
2643 
2644  verify_new_node(res);
2645  return optimize_node(res);
2646 }
2647 
2648 ir_node *new_bd_ia32_IncMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, x86_insn_size_t size)
2649 {
2650  static arch_register_req_t const *in_reqs[] = {
2651  &ia32_class_reg_req_gp,
2652  &ia32_class_reg_req_gp,
2653  &arch_memory_requirement,
2654  };
2655 
2656  /* construct in array */
2657  ir_node *const in[] = {
2658  base,
2659  index,
2660  mem,
2661  };
2662 
2663  ir_graph *const irg = get_irn_irg(block);
2664  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_IncMem, mode_T, 3, in);
2665 
2666  /* init node attributes */
2667 
2668  /* flags */
2669  arch_irn_flags_t irn_flags = arch_irn_flags_none;
2670  irn_flags |= arch_irn_flag_modify_flags;
2671  irn_flags |= arch_irn_flag_rematerializable;
2672  int const n_res = 3;
2673  be_info_init_irn(res, irn_flags, in_reqs, n_res);
2674  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
2675  (void)attr; /* avoid potential warning */
2676  init_ia32_attributes(res, size);
2677  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
2678  out_infos[0].req = &arch_no_requirement;
2679  out_infos[1].req = &ia32_class_reg_req_flags;
2680  out_infos[2].req = &arch_memory_requirement;
2681 
2682  verify_new_node(res);
2683  return optimize_node(res);
2684 }
2685 
2686 ir_node *new_bd_ia32_Inport(dbg_info *dbgi, ir_node *block, ir_node *port, ir_node *mem, x86_insn_size_t size)
2687 {
2688  static arch_register_req_t const *in_reqs[] = {
2689  &ia32_single_reg_req_gp_edx,
2690  &arch_memory_requirement,
2691  };
2692 
2693  /* construct in array */
2694  ir_node *const in[] = {
2695  port,
2696  mem,
2697  };
2698 
2699  ir_graph *const irg = get_irn_irg(block);
2700  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Inport, mode_T, 2, in);
2701 
2702  /* init node attributes */
2703 
2704  /* flags */
2705  arch_irn_flags_t irn_flags = arch_irn_flags_none;
2706  irn_flags |= arch_irn_flag_rematerializable;
2707  int const n_res = 2;
2708  be_info_init_irn(res, irn_flags, in_reqs, n_res);
2709  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
2710  (void)attr; /* avoid potential warning */
2711  init_ia32_attributes(res, size);
2712  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
2713  out_infos[0].req = &ia32_single_reg_req_gp_eax;
2714  out_infos[1].req = &arch_memory_requirement;
2715 
2716  verify_new_node(res);
2717  return optimize_node(res);
2718 }
2719 
2720 ir_node *new_bd_ia32_Jcc(dbg_info *dbgi, ir_node *block, ir_node *eflags, x86_condition_code_t condition_code)
2721 {
2722  static arch_register_req_t const *in_reqs[] = {
2723  &ia32_class_reg_req_flags,
2724  };
2725 
2726  /* construct in array */
2727  ir_node *const in[] = {
2728  eflags,
2729  };
2730 
2731  ir_graph *const irg = get_irn_irg(block);
2732  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Jcc, mode_T, 1, in);
2733 
2734  /* init node attributes */
2735 
2736  /* flags */
2737  arch_irn_flags_t irn_flags = arch_irn_flags_none;
2738  irn_flags |= arch_irn_flag_fallthrough;
2739  int const n_res = 2;
2740  be_info_init_irn(res, irn_flags, in_reqs, n_res);
2741  ia32_condcode_attr_t *const attr = (ia32_condcode_attr_t*)get_irn_generic_attr(res);
2742  (void)attr; /* avoid potential warning */
2743  x86_insn_size_t const size = X86_SIZE_32;
2744  init_ia32_attributes(res, size);
2745  init_ia32_condcode_attributes(res, condition_code);
2746  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
2747  out_infos[0].req = &arch_exec_requirement;
2748  out_infos[1].req = &arch_exec_requirement;
2749 
2750  verify_new_node(res);
2751  return optimize_node(res);
2752 }
2753 
2754 ir_node *new_bd_ia32_Jmp(dbg_info *dbgi, ir_node *block)
2755 {
2756  arch_register_req_t const **const in_reqs = NULL;
2757 
2758 
2759  ir_graph *const irg = get_irn_irg(block);
2760  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Jmp, mode_X, 0, NULL);
2761 
2762  /* init node attributes */
2763 
2764  /* flags */
2765  arch_irn_flags_t irn_flags = arch_irn_flags_none;
2766  irn_flags |= arch_irn_flag_simple_jump;
2767  irn_flags |= arch_irn_flag_fallthrough;
2768  int const n_res = 1;
2769  be_info_init_irn(res, irn_flags, in_reqs, n_res);
2770  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
2771  (void)attr; /* avoid potential warning */
2772  x86_insn_size_t const size = X86_SIZE_32;
2773  init_ia32_attributes(res, size);
2774  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
2775  out_infos[0].req = &arch_exec_requirement;
2776 
2777  verify_new_node(res);
2778  return optimize_node(res);
2779 }
2780 
2781 ir_node *new_bd_ia32_LdTls(dbg_info *dbgi, ir_node *block)
2782 {
2783  arch_register_req_t const **const in_reqs = NULL;
2784 
2785 
2786  ir_graph *const irg = get_irn_irg(block);
2787  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_LdTls, ia32_mode_gp, 0, NULL);
2788 
2789  /* init node attributes */
2790 
2791  /* flags */
2792  arch_irn_flags_t irn_flags = arch_irn_flags_none;
2793  irn_flags |= arch_irn_flag_rematerializable;
2794  int const n_res = 1;
2795  be_info_init_irn(res, irn_flags, in_reqs, n_res);
2796  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
2797  (void)attr; /* avoid potential warning */
2798  x86_insn_size_t const size = X86_SIZE_32;
2799  init_ia32_attributes(res, size);
2800  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
2801  out_infos[0].req = &ia32_class_reg_req_gp;
2802 
2803  verify_new_node(res);
2804  return optimize_node(res);
2805 }
2806 
2807 ir_node *new_bd_ia32_Lea(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index)
2808 {
2809  static arch_register_req_t const *in_reqs[] = {
2810  &ia32_class_reg_req_gp,
2811  &ia32_class_reg_req_gp,
2812  };
2813 
2814  /* construct in array */
2815  ir_node *const in[] = {
2816  base,
2817  index,
2818  };
2819 
2820  ir_graph *const irg = get_irn_irg(block);
2821  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Lea, ia32_mode_gp, 2, in);
2822 
2823  /* init node attributes */
2824 
2825  /* flags */
2826  arch_irn_flags_t irn_flags = arch_irn_flags_none;
2827  irn_flags |= arch_irn_flag_modify_flags;
2828  irn_flags |= arch_irn_flag_rematerializable;
2829  int const n_res = 1;
2830  be_info_init_irn(res, irn_flags, in_reqs, n_res);
2831  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
2832  (void)attr; /* avoid potential warning */
2833  x86_insn_size_t const size = X86_SIZE_32;
2834  init_ia32_attributes(res, size);
2835  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
2836  out_infos[0].req = &ia32_class_reg_req_gp;
2837 
2838  verify_new_node(res);
2839  return optimize_node(res);
2840 }
2841 
2842 ir_node *new_bd_ia32_Leave(dbg_info *dbgi, ir_node *block, ir_node *op0, ir_node *op1)
2843 {
2844  static arch_register_req_t const *in_reqs[] = {
2845  &arch_memory_requirement,
2846  &ia32_single_reg_req_gp_ebp,
2847  };
2848 
2849  /* construct in array */
2850  ir_node *const in[] = {
2851  op0,
2852  op1,
2853  };
2854 
2855  ir_graph *const irg = get_irn_irg(block);
2856  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Leave, mode_T, 2, in);
2857 
2858  /* init node attributes */
2859 
2860  /* flags */
2861  arch_irn_flags_t irn_flags = arch_irn_flags_none;
2862  int const n_res = 3;
2863  be_info_init_irn(res, irn_flags, in_reqs, n_res);
2864  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
2865  (void)attr; /* avoid potential warning */
2866  x86_insn_size_t const size = X86_SIZE_32;
2867  init_ia32_attributes(res, size);
2868  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
2869  out_infos[0].req = &ia32_requirements_gp_ebp_I;
2870  out_infos[1].req = &arch_memory_requirement;
2871  out_infos[2].req = &ia32_requirements_gp_esp_I;
2872 
2873  verify_new_node(res);
2874  return optimize_node(res);
2875 }
2876 
2877 ir_node *new_bd_ia32_Load(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, x86_insn_size_t size, bool sign_extend)
2878 {
2879  static arch_register_req_t const *in_reqs[] = {
2880  &ia32_class_reg_req_gp,
2881  &ia32_class_reg_req_gp,
2882  &arch_memory_requirement,
2883  };
2884 
2885  /* construct in array */
2886  ir_node *const in[] = {
2887  base,
2888  index,
2889  mem,
2890  };
2891 
2892  ir_graph *const irg = get_irn_irg(block);
2893  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Load, mode_T, 3, in);
2894 
2895  /* init node attributes */
2896 
2897  /* flags */
2898  arch_irn_flags_t irn_flags = arch_irn_flags_none;
2899  int const n_res = 5;
2900  be_info_init_irn(res, irn_flags, in_reqs, n_res);
2901  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
2902  (void)attr; /* avoid potential warning */
2903  init_ia32_attributes(res, size);
2904  attr->sign_extend = sign_extend;
2905  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
2906  out_infos[0].req = &ia32_class_reg_req_gp;
2907  out_infos[1].req = &arch_no_requirement;
2908  out_infos[2].req = &arch_memory_requirement;
2909  out_infos[3].req = &arch_exec_requirement;
2910  out_infos[4].req = &arch_exec_requirement;
2911 
2912  verify_new_node(res);
2913  return optimize_node(res);
2914 }
2915 
2916 ir_node *new_bd_ia32_Maxs(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size)
2917 {
2918  static arch_register_req_t const *in_reqs[] = {
2919  &ia32_class_reg_req_gp,
2920  &ia32_class_reg_req_gp,
2921  &arch_memory_requirement,
2922  &ia32_class_reg_req_xmm,
2923  &ia32_class_reg_req_xmm,
2924  };
2925 
2926  /* construct in array */
2927  ir_node *const in[] = {
2928  base,
2929  index,
2930  mem,
2931  left,
2932  right,
2933  };
2934 
2935  ir_graph *const irg = get_irn_irg(block);
2936  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Maxs, ia32_mode_float64, 5, in);
2937 
2938  /* init node attributes */
2939 
2940  /* flags */
2941  arch_irn_flags_t irn_flags = arch_irn_flags_none;
2942  irn_flags |= arch_irn_flag_rematerializable;
2943  int const n_res = 3;
2944  be_info_init_irn(res, irn_flags, in_reqs, n_res);
2945  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
2946  (void)attr; /* avoid potential warning */
2947  init_ia32_attributes(res, size);
2948  set_ia32_am_support(res, ia32_am_binary);
2949  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
2950  out_infos[0].req = &ia32_requirements_xmm_in_r3_in_r4;
2951  out_infos[1].req = &ia32_class_reg_req_flags;
2952  out_infos[2].req = &arch_memory_requirement;
2953 
2954  verify_new_node(res);
2955  return optimize_node(res);
2956 }
2957 
2958 ir_node *new_bd_ia32_Mins(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size)
2959 {
2960  static arch_register_req_t const *in_reqs[] = {
2961  &ia32_class_reg_req_gp,
2962  &ia32_class_reg_req_gp,
2963  &arch_memory_requirement,
2964  &ia32_class_reg_req_xmm,
2965  &ia32_class_reg_req_xmm,
2966  };
2967 
2968  /* construct in array */
2969  ir_node *const in[] = {
2970  base,
2971  index,
2972  mem,
2973  left,
2974  right,
2975  };
2976 
2977  ir_graph *const irg = get_irn_irg(block);
2978  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Mins, ia32_mode_float64, 5, in);
2979 
2980  /* init node attributes */
2981 
2982  /* flags */
2983  arch_irn_flags_t irn_flags = arch_irn_flags_none;
2984  irn_flags |= arch_irn_flag_rematerializable;
2985  int const n_res = 3;
2986  be_info_init_irn(res, irn_flags, in_reqs, n_res);
2987  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
2988  (void)attr; /* avoid potential warning */
2989  init_ia32_attributes(res, size);
2990  set_ia32_am_support(res, ia32_am_binary);
2991  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
2992  out_infos[0].req = &ia32_requirements_xmm_in_r3_in_r4;
2993  out_infos[1].req = &ia32_class_reg_req_flags;
2994  out_infos[2].req = &arch_memory_requirement;
2995 
2996  verify_new_node(res);
2997  return optimize_node(res);
2998 }
2999 
3000 ir_node *new_bd_ia32_Minus64(dbg_info *dbgi, ir_node *block, ir_node *low, ir_node *high)
3001 {
3002  static arch_register_req_t const *in_reqs[] = {
3003  &ia32_class_reg_req_gp,
3004  &ia32_class_reg_req_gp,
3005  };
3006 
3007  /* construct in array */
3008  ir_node *const in[] = {
3009  low,
3010  high,
3011  };
3012 
3013  ir_graph *const irg = get_irn_irg(block);
3014  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Minus64, mode_T, 2, in);
3015 
3016  /* init node attributes */
3017 
3018  /* flags */
3019  arch_irn_flags_t irn_flags = arch_irn_flags_none;
3020  irn_flags |= arch_irn_flag_modify_flags;
3021  irn_flags |= arch_irn_flag_rematerializable;
3022  int const n_res = 2;
3023  be_info_init_irn(res, irn_flags, in_reqs, n_res);
3024  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
3025  (void)attr; /* avoid potential warning */
3026  x86_insn_size_t const size = X86_SIZE_32;
3027  init_ia32_attributes(res, size);
3028  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
3029  out_infos[0].req = &ia32_requirements_gp_in_r0;
3030  out_infos[1].req = &ia32_requirements_gp_in_r1;
3031 
3032  verify_new_node(res);
3033  return optimize_node(res);
3034 }
3035 
3036 ir_node *new_bd_ia32_Movd(dbg_info *dbgi, ir_node *block, ir_node *op0)
3037 {
3038  static arch_register_req_t const *in_reqs[] = {
3039  &ia32_class_reg_req_gp,
3040  };
3041 
3042  /* construct in array */
3043  ir_node *const in[] = {
3044  op0,
3045  };
3046 
3047  ir_graph *const irg = get_irn_irg(block);
3048  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Movd, ia32_mode_float64, 1, in);
3049 
3050  /* init node attributes */
3051 
3052  /* flags */
3053  arch_irn_flags_t irn_flags = arch_irn_flags_none;
3054  irn_flags |= arch_irn_flag_rematerializable;
3055  int const n_res = 1;
3056  be_info_init_irn(res, irn_flags, in_reqs, n_res);
3057  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
3058  (void)attr; /* avoid potential warning */
3059  x86_insn_size_t const size = X86_SIZE_32;
3060  init_ia32_attributes(res, size);
3061  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
3062  out_infos[0].req = &ia32_class_reg_req_xmm;
3063 
3064  verify_new_node(res);
3065  return optimize_node(res);
3066 }
3067 
3068 ir_node *new_bd_ia32_Mul(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size)
3069 {
3070  static arch_register_req_t const *in_reqs[] = {
3071  &ia32_class_reg_req_gp,
3072  &ia32_class_reg_req_gp,
3073  &arch_memory_requirement,
3074  &ia32_single_reg_req_gp_eax,
3075  &ia32_class_reg_req_gp,
3076  };
3077 
3078  /* construct in array */
3079  ir_node *const in[] = {
3080  base,
3081  index,
3082  mem,
3083  left,
3084  right,
3085  };
3086 
3087  ir_graph *const irg = get_irn_irg(block);
3088  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Mul, mode_T, 5, in);
3089 
3090  /* init node attributes */
3091 
3092  /* flags */
3093  arch_irn_flags_t irn_flags = arch_irn_flags_none;
3094  irn_flags |= arch_irn_flag_modify_flags;
3095  int const n_res = 4;
3096  be_info_init_irn(res, irn_flags, in_reqs, n_res);
3097  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
3098  (void)attr; /* avoid potential warning */
3099  init_ia32_attributes(res, size);
3100  set_ia32_am_support(res, ia32_am_binary);
3101  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
3102  out_infos[0].req = &ia32_single_reg_req_gp_eax;
3103  out_infos[1].req = &ia32_class_reg_req_flags;
3104  out_infos[2].req = &arch_memory_requirement;
3105  out_infos[3].req = &ia32_single_reg_req_gp_edx;
3106 
3107  verify_new_node(res);
3108  return optimize_node(res);
3109 }
3110 
3111 ir_node *new_bd_ia32_Muls(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size)
3112 {
3113  static arch_register_req_t const *in_reqs[] = {
3114  &ia32_class_reg_req_gp,
3115  &ia32_class_reg_req_gp,
3116  &arch_memory_requirement,
3117  &ia32_class_reg_req_xmm,
3118  &ia32_class_reg_req_xmm,
3119  };
3120 
3121  /* construct in array */
3122  ir_node *const in[] = {
3123  base,
3124  index,
3125  mem,
3126  left,
3127  right,
3128  };
3129 
3130  ir_graph *const irg = get_irn_irg(block);
3131  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Muls, ia32_mode_float64, 5, in);
3132 
3133  /* init node attributes */
3134 
3135  /* flags */
3136  arch_irn_flags_t irn_flags = arch_irn_flags_none;
3137  irn_flags |= arch_irn_flag_rematerializable;
3138  int const n_res = 3;
3139  be_info_init_irn(res, irn_flags, in_reqs, n_res);
3140  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
3141  (void)attr; /* avoid potential warning */
3142  init_ia32_attributes(res, size);
3143  set_ia32_am_support(res, ia32_am_binary);
3144  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
3145  out_infos[0].req = &ia32_requirements_xmm_in_r3_in_r4;
3146  out_infos[1].req = &ia32_class_reg_req_flags;
3147  out_infos[2].req = &arch_memory_requirement;
3148 
3149  verify_new_node(res);
3150  return optimize_node(res);
3151 }
3152 
3153 ir_node *new_bd_ia32_Neg(dbg_info *dbgi, ir_node *block, ir_node *val, x86_insn_size_t size)
3154 {
3155  static arch_register_req_t const *in_reqs[] = {
3156  &ia32_class_reg_req_gp,
3157  };
3158 
3159  /* construct in array */
3160  ir_node *const in[] = {
3161  val,
3162  };
3163 
3164  ir_graph *const irg = get_irn_irg(block);
3165  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Neg, ia32_mode_gp, 1, in);
3166 
3167  /* init node attributes */
3168 
3169  /* flags */
3170  arch_irn_flags_t irn_flags = arch_irn_flags_none;
3171  irn_flags |= arch_irn_flag_modify_flags;
3172  irn_flags |= arch_irn_flag_rematerializable;
3173  int const n_res = 2;
3174  be_info_init_irn(res, irn_flags, in_reqs, n_res);
3175  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
3176  (void)attr; /* avoid potential warning */
3177  init_ia32_attributes(res, size);
3178  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
3179  out_infos[0].req = &ia32_requirements_gp_in_r0;
3180  out_infos[1].req = &ia32_class_reg_req_flags;
3181 
3182  verify_new_node(res);
3183  return optimize_node(res);
3184 }
3185 
3186 ir_node *new_bd_ia32_NegMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, x86_insn_size_t size)
3187 {
3188  static arch_register_req_t const *in_reqs[] = {
3189  &ia32_class_reg_req_gp,
3190  &ia32_class_reg_req_gp,
3191  &arch_memory_requirement,
3192  };
3193 
3194  /* construct in array */
3195  ir_node *const in[] = {
3196  base,
3197  index,
3198  mem,
3199  };
3200 
3201  ir_graph *const irg = get_irn_irg(block);
3202  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_NegMem, mode_T, 3, in);
3203 
3204  /* init node attributes */
3205 
3206  /* flags */
3207  arch_irn_flags_t irn_flags = arch_irn_flags_none;
3208  irn_flags |= arch_irn_flag_modify_flags;
3209  irn_flags |= arch_irn_flag_rematerializable;
3210  int const n_res = 3;
3211  be_info_init_irn(res, irn_flags, in_reqs, n_res);
3212  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
3213  (void)attr; /* avoid potential warning */
3214  init_ia32_attributes(res, size);
3215  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
3216  out_infos[0].req = &arch_no_requirement;
3217  out_infos[1].req = &ia32_class_reg_req_flags;
3218  out_infos[2].req = &arch_memory_requirement;
3219 
3220  verify_new_node(res);
3221  return optimize_node(res);
3222 }
3223 
3224 ir_node *new_bd_ia32_NoReg_FP(dbg_info *dbgi, ir_node *block)
3225 {
3226  arch_register_req_t const **const in_reqs = NULL;
3227 
3228 
3229  ir_graph *const irg = get_irn_irg(block);
3230  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_NoReg_FP, x86_mode_E, 0, NULL);
3231 
3232  /* init node attributes */
3233 
3234  /* flags */
3235  arch_irn_flags_t irn_flags = arch_irn_flags_none;
3236  irn_flags |= arch_irn_flag_not_scheduled;
3237  int const n_res = 1;
3238  be_info_init_irn(res, irn_flags, in_reqs, n_res);
3239  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
3240  (void)attr; /* avoid potential warning */
3241  x86_insn_size_t const size = X86_SIZE_32;
3242  ia32_request_x87_sim(irg);
3243  init_ia32_attributes(res, size);
3244  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
3245  out_infos[0].req = &ia32_requirements_fp_fp_NOREG_I;
3246 
3247  verify_new_node(res);
3248  return optimize_node(res);
3249 }
3250 
3251 ir_node *new_bd_ia32_NoReg_GP(dbg_info *dbgi, ir_node *block)
3252 {
3253  arch_register_req_t const **const in_reqs = NULL;
3254 
3255 
3256  ir_graph *const irg = get_irn_irg(block);
3257  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_NoReg_GP, ia32_mode_gp, 0, NULL);
3258 
3259  /* init node attributes */
3260 
3261  /* flags */
3262  arch_irn_flags_t irn_flags = arch_irn_flags_none;
3263  irn_flags |= arch_irn_flag_not_scheduled;
3264  int const n_res = 1;
3265  be_info_init_irn(res, irn_flags, in_reqs, n_res);
3266  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
3267  (void)attr; /* avoid potential warning */
3268  x86_insn_size_t const size = X86_SIZE_32;
3269  init_ia32_attributes(res, size);
3270  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
3271  out_infos[0].req = &ia32_requirements_gp_gp_NOREG_I;
3272 
3273  verify_new_node(res);
3274  return optimize_node(res);
3275 }
3276 
3277 ir_node *new_bd_ia32_NoReg_XMM(dbg_info *dbgi, ir_node *block)
3278 {
3279  arch_register_req_t const **const in_reqs = NULL;
3280 
3281 
3282  ir_graph *const irg = get_irn_irg(block);
3283  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_NoReg_XMM, ia32_mode_float64, 0, NULL);
3284 
3285  /* init node attributes */
3286 
3287  /* flags */
3288  arch_irn_flags_t irn_flags = arch_irn_flags_none;
3289  irn_flags |= arch_irn_flag_not_scheduled;
3290  int const n_res = 1;
3291  be_info_init_irn(res, irn_flags, in_reqs, n_res);
3292  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
3293  (void)attr; /* avoid potential warning */
3294  x86_insn_size_t const size = X86_SIZE_32;
3295  init_ia32_attributes(res, size);
3296  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
3297  out_infos[0].req = &ia32_requirements_xmm_xmm_NOREG_I;
3298 
3299  verify_new_node(res);
3300  return optimize_node(res);
3301 }
3302 
3303 ir_node *new_bd_ia32_Not(dbg_info *dbgi, ir_node *block, ir_node *val, x86_insn_size_t size)
3304 {
3305  static arch_register_req_t const *in_reqs[] = {
3306  &ia32_class_reg_req_gp,
3307  };
3308 
3309  /* construct in array */
3310  ir_node *const in[] = {
3311  val,
3312  };
3313 
3314  ir_graph *const irg = get_irn_irg(block);
3315  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Not, ia32_mode_gp, 1, in);
3316 
3317  /* init node attributes */
3318 
3319  /* flags */
3320  arch_irn_flags_t irn_flags = arch_irn_flags_none;
3321  irn_flags |= arch_irn_flag_rematerializable;
3322  int const n_res = 1;
3323  be_info_init_irn(res, irn_flags, in_reqs, n_res);
3324  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
3325  (void)attr; /* avoid potential warning */
3326  init_ia32_attributes(res, size);
3327  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
3328  out_infos[0].req = &ia32_requirements_gp_in_r0;
3329 
3330  verify_new_node(res);
3331  return optimize_node(res);
3332 }
3333 
3334 ir_node *new_bd_ia32_Not_8bit(dbg_info *dbgi, ir_node *block, ir_node *val, x86_insn_size_t size)
3335 {
3336  static arch_register_req_t const *in_reqs[] = {
3337  &ia32_requirements_gp_eax_ebx_ecx_edx,
3338  };
3339 
3340  /* construct in array */
3341  ir_node *const in[] = {
3342  val,
3343  };
3344 
3345  ir_graph *const irg = get_irn_irg(block);
3346  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Not, ia32_mode_gp, 1, in);
3347 
3348  /* init node attributes */
3349 
3350  /* flags */
3351  arch_irn_flags_t irn_flags = arch_irn_flags_none;
3352  irn_flags |= arch_irn_flag_rematerializable;
3353  int const n_res = 1;
3354  be_info_init_irn(res, irn_flags, in_reqs, n_res);
3355  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
3356  (void)attr; /* avoid potential warning */
3357  init_ia32_attributes(res, size);
3358  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
3359  out_infos[0].req = &ia32_requirements_gp_in_r0;
3360 
3361  verify_new_node(res);
3362  return optimize_node(res);
3363 }
3364 
3365 ir_node *new_bd_ia32_NotMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, x86_insn_size_t size)
3366 {
3367  static arch_register_req_t const *in_reqs[] = {
3368  &ia32_class_reg_req_gp,
3369  &ia32_class_reg_req_gp,
3370  &arch_memory_requirement,
3371  };
3372 
3373  /* construct in array */
3374  ir_node *const in[] = {
3375  base,
3376  index,
3377  mem,
3378  };
3379 
3380  ir_graph *const irg = get_irn_irg(block);
3381  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_NotMem, mode_T, 3, in);
3382 
3383  /* init node attributes */
3384 
3385  /* flags */
3386  arch_irn_flags_t irn_flags = arch_irn_flags_none;
3387  irn_flags |= arch_irn_flag_rematerializable;
3388  int const n_res = 3;
3389  be_info_init_irn(res, irn_flags, in_reqs, n_res);
3390  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
3391  (void)attr; /* avoid potential warning */
3392  init_ia32_attributes(res, size);
3393  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
3394  out_infos[0].req = &arch_no_requirement;
3395  out_infos[1].req = &arch_no_requirement;
3396  out_infos[2].req = &arch_memory_requirement;
3397 
3398  verify_new_node(res);
3399  return optimize_node(res);
3400 }
3401 
3402 ir_node *new_bd_ia32_Or(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size)
3403 {
3404  static arch_register_req_t const *in_reqs[] = {
3405  &ia32_class_reg_req_gp,
3406  &ia32_class_reg_req_gp,
3407  &arch_memory_requirement,
3408  &ia32_class_reg_req_gp,
3409  &ia32_class_reg_req_gp,
3410  };
3411 
3412  /* construct in array */
3413  ir_node *const in[] = {
3414  base,
3415  index,
3416  mem,
3417  left,
3418  right,
3419  };
3420 
3421  ir_graph *const irg = get_irn_irg(block);
3422  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Or, ia32_mode_gp, 5, in);
3423 
3424  /* init node attributes */
3425 
3426  /* flags */
3427  arch_irn_flags_t irn_flags = arch_irn_flags_none;
3428  irn_flags |= arch_irn_flag_modify_flags;
3429  irn_flags |= arch_irn_flag_rematerializable;
3430  int const n_res = 3;
3431  be_info_init_irn(res, irn_flags, in_reqs, n_res);
3432  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
3433  (void)attr; /* avoid potential warning */
3434  init_ia32_attributes(res, size);
3435  set_ia32_am_support(res, ia32_am_binary);
3436  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
3437  out_infos[0].req = &ia32_requirements_gp_in_r3_in_r4;
3438  out_infos[1].req = &ia32_class_reg_req_flags;
3439  out_infos[2].req = &arch_memory_requirement;
3440 
3441  verify_new_node(res);
3442  return optimize_node(res);
3443 }
3444 
3445 ir_node *new_bd_ia32_Or_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size)
3446 {
3447  static arch_register_req_t const *in_reqs[] = {
3448  &ia32_class_reg_req_gp,
3449  &ia32_class_reg_req_gp,
3450  &arch_memory_requirement,
3451  &ia32_requirements_gp_eax_ebx_ecx_edx,
3452  &ia32_requirements_gp_eax_ebx_ecx_edx,
3453  };
3454 
3455  /* construct in array */
3456  ir_node *const in[] = {
3457  base,
3458  index,
3459  mem,
3460  left,
3461  right,
3462  };
3463 
3464  ir_graph *const irg = get_irn_irg(block);
3465  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Or, ia32_mode_gp, 5, in);
3466 
3467  /* init node attributes */
3468 
3469  /* flags */
3470  arch_irn_flags_t irn_flags = arch_irn_flags_none;
3471  irn_flags |= arch_irn_flag_modify_flags;
3472  irn_flags |= arch_irn_flag_rematerializable;
3473  int const n_res = 3;
3474  be_info_init_irn(res, irn_flags, in_reqs, n_res);
3475  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
3476  (void)attr; /* avoid potential warning */
3477  init_ia32_attributes(res, size);
3478  set_ia32_am_support(res, ia32_am_binary);
3479  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
3480  out_infos[0].req = &ia32_requirements_gp_eax_ebx_ecx_edx_in_r3_in_r4;
3481  out_infos[1].req = &ia32_class_reg_req_flags;
3482  out_infos[2].req = &arch_memory_requirement;
3483 
3484  verify_new_node(res);
3485  return optimize_node(res);
3486 }
3487 
3488 ir_node *new_bd_ia32_OrMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size)
3489 {
3490  static arch_register_req_t const *in_reqs[] = {
3491  &ia32_class_reg_req_gp,
3492  &ia32_class_reg_req_gp,
3493  &arch_memory_requirement,
3494  &ia32_class_reg_req_gp,
3495  };
3496 
3497  /* construct in array */
3498  ir_node *const in[] = {
3499  base,
3500  index,
3501  mem,
3502  val,
3503  };
3504 
3505  ir_graph *const irg = get_irn_irg(block);
3506  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_OrMem, mode_T, 4, in);
3507 
3508  /* init node attributes */
3509 
3510  /* flags */
3511  arch_irn_flags_t irn_flags = arch_irn_flags_none;
3512  irn_flags |= arch_irn_flag_modify_flags;
3513  irn_flags |= arch_irn_flag_rematerializable;
3514  int const n_res = 3;
3515  be_info_init_irn(res, irn_flags, in_reqs, n_res);
3516  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
3517  (void)attr; /* avoid potential warning */
3518  init_ia32_attributes(res, size);
3519  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
3520  out_infos[0].req = &arch_no_requirement;
3521  out_infos[1].req = &ia32_class_reg_req_flags;
3522  out_infos[2].req = &arch_memory_requirement;
3523 
3524  verify_new_node(res);
3525  return optimize_node(res);
3526 }
3527 
3528 ir_node *new_bd_ia32_OrMem_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size)
3529 {
3530  static arch_register_req_t const *in_reqs[] = {
3531  &ia32_class_reg_req_gp,
3532  &ia32_class_reg_req_gp,
3533  &arch_memory_requirement,
3534  &ia32_requirements_gp_eax_ebx_ecx_edx,
3535  };
3536 
3537  /* construct in array */
3538  ir_node *const in[] = {
3539  base,
3540  index,
3541  mem,
3542  val,
3543  };
3544 
3545  ir_graph *const irg = get_irn_irg(block);
3546  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_OrMem, mode_T, 4, in);
3547 
3548  /* init node attributes */
3549 
3550  /* flags */
3551  arch_irn_flags_t irn_flags = arch_irn_flags_none;
3552  irn_flags |= arch_irn_flag_modify_flags;
3553  irn_flags |= arch_irn_flag_rematerializable;
3554  int const n_res = 3;
3555  be_info_init_irn(res, irn_flags, in_reqs, n_res);
3556  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
3557  (void)attr; /* avoid potential warning */
3558  init_ia32_attributes(res, size);
3559  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
3560  out_infos[0].req = &arch_no_requirement;
3561  out_infos[1].req = &ia32_class_reg_req_flags;
3562  out_infos[2].req = &arch_memory_requirement;
3563 
3564  verify_new_node(res);
3565  return optimize_node(res);
3566 }
3567 
3568 ir_node *new_bd_ia32_Orp(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size)
3569 {
3570  static arch_register_req_t const *in_reqs[] = {
3571  &ia32_class_reg_req_gp,
3572  &ia32_class_reg_req_gp,
3573  &arch_memory_requirement,
3574  &ia32_class_reg_req_xmm,
3575  &ia32_class_reg_req_xmm,
3576  };
3577 
3578  /* construct in array */
3579  ir_node *const in[] = {
3580  base,
3581  index,
3582  mem,
3583  left,
3584  right,
3585  };
3586 
3587  ir_graph *const irg = get_irn_irg(block);
3588  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Orp, ia32_mode_float64, 5, in);
3589 
3590  /* init node attributes */
3591 
3592  /* flags */
3593  arch_irn_flags_t irn_flags = arch_irn_flags_none;
3594  irn_flags |= arch_irn_flag_rematerializable;
3595  int const n_res = 3;
3596  be_info_init_irn(res, irn_flags, in_reqs, n_res);
3597  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
3598  (void)attr; /* avoid potential warning */
3599  init_ia32_attributes(res, size);
3600  set_ia32_am_support(res, ia32_am_binary);
3601  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
3602  out_infos[0].req = &ia32_requirements_xmm_in_r3_in_r4;
3603  out_infos[1].req = &ia32_class_reg_req_flags;
3604  out_infos[2].req = &arch_memory_requirement;
3605 
3606  verify_new_node(res);
3607  return optimize_node(res);
3608 }
3609 
3610 ir_node *new_bd_ia32_Outport(dbg_info *dbgi, ir_node *block, ir_node *port, ir_node *value, ir_node *mem, x86_insn_size_t size)
3611 {
3612  static arch_register_req_t const *in_reqs[] = {
3613  &ia32_single_reg_req_gp_edx,
3614  &ia32_single_reg_req_gp_eax,
3615  &arch_memory_requirement,
3616  };
3617 
3618  /* construct in array */
3619  ir_node *const in[] = {
3620  port,
3621  value,
3622  mem,
3623  };
3624 
3625  ir_graph *const irg = get_irn_irg(block);
3626  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Outport, mode_M, 3, in);
3627 
3628  /* init node attributes */
3629 
3630  /* flags */
3631  arch_irn_flags_t irn_flags = arch_irn_flags_none;
3632  irn_flags |= arch_irn_flag_rematerializable;
3633  int const n_res = 1;
3634  be_info_init_irn(res, irn_flags, in_reqs, n_res);
3635  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
3636  (void)attr; /* avoid potential warning */
3637  init_ia32_attributes(res, size);
3638  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
3639  out_infos[0].req = &arch_memory_requirement;
3640 
3641  verify_new_node(res);
3642  return optimize_node(res);
3643 }
3644 
3645 ir_node *new_bd_ia32_Pop(dbg_info *dbgi, ir_node *block, ir_node *mem, ir_node *stack, x86_insn_size_t size)
3646 {
3647  static arch_register_req_t const *in_reqs[] = {
3648  &arch_memory_requirement,
3649  &ia32_single_reg_req_gp_esp,
3650  };
3651 
3652  /* construct in array */
3653  ir_node *const in[] = {
3654  mem,
3655  stack,
3656  };
3657 
3658  ir_graph *const irg = get_irn_irg(block);
3659  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Pop, mode_T, 2, in);
3660 
3661  /* init node attributes */
3662 
3663  /* flags */
3664  arch_irn_flags_t irn_flags = arch_irn_flags_none;
3665  int const n_res = 4;
3666  be_info_init_irn(res, irn_flags, in_reqs, n_res);
3667  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
3668  (void)attr; /* avoid potential warning */
3669  init_ia32_attributes(res, size);
3670  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
3671  out_infos[0].req = &ia32_class_reg_req_gp;
3672  out_infos[1].req = &arch_no_requirement;
3673  out_infos[2].req = &arch_memory_requirement;
3674  out_infos[3].req = &ia32_requirements_gp_esp_I;
3675 
3676  verify_new_node(res);
3677  return optimize_node(res);
3678 }
3679 
3680 ir_node *new_bd_ia32_Pop_ebp(dbg_info *dbgi, ir_node *block, ir_node *mem, ir_node *stack, x86_insn_size_t size)
3681 {
3682  static arch_register_req_t const *in_reqs[] = {
3683  &arch_memory_requirement,
3684  &ia32_single_reg_req_gp_esp,
3685  };
3686 
3687  /* construct in array */
3688  ir_node *const in[] = {
3689  mem,
3690  stack,
3691  };
3692 
3693  ir_graph *const irg = get_irn_irg(block);
3694  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Pop, mode_T, 2, in);
3695 
3696  /* init node attributes */
3697 
3698  /* flags */
3699  arch_irn_flags_t irn_flags = arch_irn_flags_none;
3700  int const n_res = 4;
3701  be_info_init_irn(res, irn_flags, in_reqs, n_res);
3702  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
3703  (void)attr; /* avoid potential warning */
3704  init_ia32_attributes(res, size);
3705  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
3706  out_infos[0].req = &ia32_requirements_gp_ebp_I;
3707  out_infos[1].req = &arch_no_requirement;
3708  out_infos[2].req = &arch_memory_requirement;
3709  out_infos[3].req = &ia32_requirements_gp_esp_I;
3710 
3711  verify_new_node(res);
3712  return optimize_node(res);
3713 }
3714 
3715 ir_node *new_bd_ia32_PopMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *stack, x86_insn_size_t size)
3716 {
3717  static arch_register_req_t const *in_reqs[] = {
3718  &ia32_class_reg_req_gp,
3719  &ia32_class_reg_req_gp,
3720  &arch_memory_requirement,
3721  &ia32_single_reg_req_gp_esp,
3722  };
3723 
3724  /* construct in array */
3725  ir_node *const in[] = {
3726  base,
3727  index,
3728  mem,
3729  stack,
3730  };
3731 
3732  ir_graph *const irg = get_irn_irg(block);
3733  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_PopMem, mode_T, 4, in);
3734 
3735  /* init node attributes */
3736 
3737  /* flags */
3738  arch_irn_flags_t irn_flags = arch_irn_flags_none;
3739  int const n_res = 4;
3740  be_info_init_irn(res, irn_flags, in_reqs, n_res);
3741  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
3742  (void)attr; /* avoid potential warning */
3743  init_ia32_attributes(res, size);
3744  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
3745  out_infos[0].req = &arch_no_requirement;
3746  out_infos[1].req = &arch_no_requirement;
3747  out_infos[2].req = &arch_memory_requirement;
3748  out_infos[3].req = &ia32_requirements_gp_esp_I;
3749 
3750  verify_new_node(res);
3751  return optimize_node(res);
3752 }
3753 
3754 ir_node *new_bd_ia32_Popcnt(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *operand, x86_insn_size_t size)
3755 {
3756  static arch_register_req_t const *in_reqs[] = {
3757  &ia32_class_reg_req_gp,
3758  &ia32_class_reg_req_gp,
3759  &arch_memory_requirement,
3760  &ia32_class_reg_req_gp,
3761  };
3762 
3763  /* construct in array */
3764  ir_node *const in[] = {
3765  base,
3766  index,
3767  mem,
3768  operand,
3769  };
3770 
3771  ir_graph *const irg = get_irn_irg(block);
3772  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Popcnt, ia32_mode_gp, 4, in);
3773 
3774  /* init node attributes */
3775 
3776  /* flags */
3777  arch_irn_flags_t irn_flags = arch_irn_flags_none;
3778  irn_flags |= arch_irn_flag_modify_flags;
3779  irn_flags |= arch_irn_flag_rematerializable;
3780  int const n_res = 3;
3781  be_info_init_irn(res, irn_flags, in_reqs, n_res);
3782  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
3783  (void)attr; /* avoid potential warning */
3784  init_ia32_attributes(res, size);
3785  set_ia32_am_support(res, ia32_am_unary);
3786  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
3787  out_infos[0].req = &ia32_class_reg_req_gp;
3788  out_infos[1].req = &ia32_class_reg_req_flags;
3789  out_infos[2].req = &arch_memory_requirement;
3790 
3791  verify_new_node(res);
3792  return optimize_node(res);
3793 }
3794 
3795 ir_node *new_bd_ia32_Prefetch(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem)
3796 {
3797  static arch_register_req_t const *in_reqs[] = {
3798  &ia32_class_reg_req_gp,
3799  &ia32_class_reg_req_gp,
3800  &arch_memory_requirement,
3801  };
3802 
3803  /* construct in array */
3804  ir_node *const in[] = {
3805  base,
3806  index,
3807  mem,
3808  };
3809 
3810  ir_graph *const irg = get_irn_irg(block);
3811  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Prefetch, mode_M, 3, in);
3812 
3813  /* init node attributes */
3814 
3815  /* flags */
3816  arch_irn_flags_t irn_flags = arch_irn_flags_none;
3817  int const n_res = 1;
3818  be_info_init_irn(res, irn_flags, in_reqs, n_res);
3819  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
3820  (void)attr; /* avoid potential warning */
3821  x86_insn_size_t const size = X86_SIZE_8;
3822  init_ia32_attributes(res, size);
3823  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
3824  out_infos[0].req = &arch_memory_requirement;
3825 
3826  verify_new_node(res);
3827  return optimize_node(res);
3828 }
3829 
3830 ir_node *new_bd_ia32_PrefetchNTA(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem)
3831 {
3832  static arch_register_req_t const *in_reqs[] = {
3833  &ia32_class_reg_req_gp,
3834  &ia32_class_reg_req_gp,
3835  &arch_memory_requirement,
3836  };
3837 
3838  /* construct in array */
3839  ir_node *const in[] = {
3840  base,
3841  index,
3842  mem,
3843  };
3844 
3845  ir_graph *const irg = get_irn_irg(block);
3846  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_PrefetchNTA, mode_M, 3, in);
3847 
3848  /* init node attributes */
3849 
3850  /* flags */
3851  arch_irn_flags_t irn_flags = arch_irn_flags_none;
3852  int const n_res = 1;
3853  be_info_init_irn(res, irn_flags, in_reqs, n_res);
3854  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
3855  (void)attr; /* avoid potential warning */
3856  x86_insn_size_t const size = X86_SIZE_8;
3857  init_ia32_attributes(res, size);
3858  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
3859  out_infos[0].req = &arch_memory_requirement;
3860 
3861  verify_new_node(res);
3862  return optimize_node(res);
3863 }
3864 
3865 ir_node *new_bd_ia32_PrefetchT0(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem)
3866 {
3867  static arch_register_req_t const *in_reqs[] = {
3868  &ia32_class_reg_req_gp,
3869  &ia32_class_reg_req_gp,
3870  &arch_memory_requirement,
3871  };
3872 
3873  /* construct in array */
3874  ir_node *const in[] = {
3875  base,
3876  index,
3877  mem,
3878  };
3879 
3880  ir_graph *const irg = get_irn_irg(block);
3881  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_PrefetchT0, mode_M, 3, in);
3882 
3883  /* init node attributes */
3884 
3885  /* flags */
3886  arch_irn_flags_t irn_flags = arch_irn_flags_none;
3887  int const n_res = 1;
3888  be_info_init_irn(res, irn_flags, in_reqs, n_res);
3889  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
3890  (void)attr; /* avoid potential warning */
3891  x86_insn_size_t const size = X86_SIZE_8;
3892  init_ia32_attributes(res, size);
3893  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
3894  out_infos[0].req = &arch_memory_requirement;
3895 
3896  verify_new_node(res);
3897  return optimize_node(res);
3898 }
3899 
3900 ir_node *new_bd_ia32_PrefetchT1(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem)
3901 {
3902  static arch_register_req_t const *in_reqs[] = {
3903  &ia32_class_reg_req_gp,
3904  &ia32_class_reg_req_gp,
3905  &arch_memory_requirement,
3906  };
3907 
3908  /* construct in array */
3909  ir_node *const in[] = {
3910  base,
3911  index,
3912  mem,
3913  };
3914 
3915  ir_graph *const irg = get_irn_irg(block);
3916  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_PrefetchT1, mode_M, 3, in);
3917 
3918  /* init node attributes */
3919 
3920  /* flags */
3921  arch_irn_flags_t irn_flags = arch_irn_flags_none;
3922  int const n_res = 1;
3923  be_info_init_irn(res, irn_flags, in_reqs, n_res);
3924  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
3925  (void)attr; /* avoid potential warning */
3926  x86_insn_size_t const size = X86_SIZE_8;
3927  init_ia32_attributes(res, size);
3928  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
3929  out_infos[0].req = &arch_memory_requirement;
3930 
3931  verify_new_node(res);
3932  return optimize_node(res);
3933 }
3934 
3935 ir_node *new_bd_ia32_PrefetchT2(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem)
3936 {
3937  static arch_register_req_t const *in_reqs[] = {
3938  &ia32_class_reg_req_gp,
3939  &ia32_class_reg_req_gp,
3940  &arch_memory_requirement,
3941  };
3942 
3943  /* construct in array */
3944  ir_node *const in[] = {
3945  base,
3946  index,
3947  mem,
3948  };
3949 
3950  ir_graph *const irg = get_irn_irg(block);
3951  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_PrefetchT2, mode_M, 3, in);
3952 
3953  /* init node attributes */
3954 
3955  /* flags */
3956  arch_irn_flags_t irn_flags = arch_irn_flags_none;
3957  int const n_res = 1;
3958  be_info_init_irn(res, irn_flags, in_reqs, n_res);
3959  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
3960  (void)attr; /* avoid potential warning */
3961  x86_insn_size_t const size = X86_SIZE_8;
3962  init_ia32_attributes(res, size);
3963  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
3964  out_infos[0].req = &arch_memory_requirement;
3965 
3966  verify_new_node(res);
3967  return optimize_node(res);
3968 }
3969 
3970 ir_node *new_bd_ia32_PrefetchW(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem)
3971 {
3972  static arch_register_req_t const *in_reqs[] = {
3973  &ia32_class_reg_req_gp,
3974  &ia32_class_reg_req_gp,
3975  &arch_memory_requirement,
3976  };
3977 
3978  /* construct in array */
3979  ir_node *const in[] = {
3980  base,
3981  index,
3982  mem,
3983  };
3984 
3985  ir_graph *const irg = get_irn_irg(block);
3986  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_PrefetchW, mode_M, 3, in);
3987 
3988  /* init node attributes */
3989 
3990  /* flags */
3991  arch_irn_flags_t irn_flags = arch_irn_flags_none;
3992  int const n_res = 1;
3993  be_info_init_irn(res, irn_flags, in_reqs, n_res);
3994  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
3995  (void)attr; /* avoid potential warning */
3996  x86_insn_size_t const size = X86_SIZE_8;
3997  init_ia32_attributes(res, size);
3998  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
3999  out_infos[0].req = &arch_memory_requirement;
4000 
4001  verify_new_node(res);
4002  return optimize_node(res);
4003 }
4004 
4005 ir_node *new_bd_ia32_Pslld(dbg_info *dbgi, ir_node *block, ir_node *op0, ir_node *op1, x86_insn_size_t size)
4006 {
4007  static arch_register_req_t const *in_reqs[] = {
4008  &ia32_class_reg_req_xmm,
4009  &ia32_class_reg_req_xmm,
4010  };
4011 
4012  /* construct in array */
4013  ir_node *const in[] = {
4014  op0,
4015  op1,
4016  };
4017 
4018  ir_graph *const irg = get_irn_irg(block);
4019  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Pslld, ia32_mode_float64, 2, in);
4020 
4021  /* init node attributes */
4022 
4023  /* flags */
4024  arch_irn_flags_t irn_flags = arch_irn_flags_none;
4025  irn_flags |= arch_irn_flag_rematerializable;
4026  int const n_res = 1;
4027  be_info_init_irn(res, irn_flags, in_reqs, n_res);
4028  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
4029  (void)attr; /* avoid potential warning */
4030  init_ia32_attributes(res, size);
4031  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
4032  out_infos[0].req = &ia32_requirements_xmm_in_r0_not_in_r1;
4033 
4034  verify_new_node(res);
4035  return optimize_node(res);
4036 }
4037 
4038 ir_node *new_bd_ia32_Psllq(dbg_info *dbgi, ir_node *block, ir_node *op0, ir_node *op1, x86_insn_size_t size)
4039 {
4040  static arch_register_req_t const *in_reqs[] = {
4041  &ia32_class_reg_req_xmm,
4042  &ia32_class_reg_req_xmm,
4043  };
4044 
4045  /* construct in array */
4046  ir_node *const in[] = {
4047  op0,
4048  op1,
4049  };
4050 
4051  ir_graph *const irg = get_irn_irg(block);
4052  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Psllq, ia32_mode_float64, 2, in);
4053 
4054  /* init node attributes */
4055 
4056  /* flags */
4057  arch_irn_flags_t irn_flags = arch_irn_flags_none;
4058  irn_flags |= arch_irn_flag_rematerializable;
4059  int const n_res = 1;
4060  be_info_init_irn(res, irn_flags, in_reqs, n_res);
4061  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
4062  (void)attr; /* avoid potential warning */
4063  init_ia32_attributes(res, size);
4064  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
4065  out_infos[0].req = &ia32_requirements_xmm_in_r0_not_in_r1;
4066 
4067  verify_new_node(res);
4068  return optimize_node(res);
4069 }
4070 
4071 ir_node *new_bd_ia32_Psrld(dbg_info *dbgi, ir_node *block, ir_node *op0, ir_node *op1, x86_insn_size_t size)
4072 {
4073  static arch_register_req_t const *in_reqs[] = {
4074  &ia32_class_reg_req_xmm,
4075  &ia32_class_reg_req_xmm,
4076  };
4077 
4078  /* construct in array */
4079  ir_node *const in[] = {
4080  op0,
4081  op1,
4082  };
4083 
4084  ir_graph *const irg = get_irn_irg(block);
4085  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Psrld, ia32_mode_float64, 2, in);
4086 
4087  /* init node attributes */
4088 
4089  /* flags */
4090  arch_irn_flags_t irn_flags = arch_irn_flags_none;
4091  irn_flags |= arch_irn_flag_rematerializable;
4092  int const n_res = 1;
4093  be_info_init_irn(res, irn_flags, in_reqs, n_res);
4094  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
4095  (void)attr; /* avoid potential warning */
4096  init_ia32_attributes(res, size);
4097  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
4098  out_infos[0].req = &ia32_requirements_xmm_in_r0_not_in_r1;
4099 
4100  verify_new_node(res);
4101  return optimize_node(res);
4102 }
4103 
4104 ir_node *new_bd_ia32_Push(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, ir_node *stack, x86_insn_size_t size)
4105 {
4106  static arch_register_req_t const *in_reqs[] = {
4107  &ia32_class_reg_req_gp,
4108  &ia32_class_reg_req_gp,
4109  &arch_memory_requirement,
4110  &ia32_class_reg_req_gp,
4111  &ia32_single_reg_req_gp_esp,
4112  };
4113 
4114  /* construct in array */
4115  ir_node *const in[] = {
4116  base,
4117  index,
4118  mem,
4119  val,
4120  stack,
4121  };
4122 
4123  ir_graph *const irg = get_irn_irg(block);
4124  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Push, mode_T, 5, in);
4125 
4126  /* init node attributes */
4127 
4128  /* flags */
4129  arch_irn_flags_t irn_flags = arch_irn_flags_none;
4130  int const n_res = 2;
4131  be_info_init_irn(res, irn_flags, in_reqs, n_res);
4132  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
4133  (void)attr; /* avoid potential warning */
4134  init_ia32_attributes(res, size);
4135  set_ia32_am_support(res, ia32_am_unary);
4136  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
4137  out_infos[0].req = &arch_memory_requirement;
4138  out_infos[1].req = &ia32_requirements_gp_esp_I;
4139 
4140  verify_new_node(res);
4141  return optimize_node(res);
4142 }
4143 
4144 ir_node *new_bd_ia32_PushEax(dbg_info *dbgi, ir_node *block, ir_node *stack)
4145 {
4146  static arch_register_req_t const *in_reqs[] = {
4147  &ia32_single_reg_req_gp_esp,
4148  };
4149 
4150  /* construct in array */
4151  ir_node *const in[] = {
4152  stack,
4153  };
4154 
4155  ir_graph *const irg = get_irn_irg(block);
4156  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_PushEax, ia32_mode_gp, 1, in);
4157 
4158  /* init node attributes */
4159 
4160  /* flags */
4161  arch_irn_flags_t irn_flags = arch_irn_flags_none;
4162  int const n_res = 1;
4163  be_info_init_irn(res, irn_flags, in_reqs, n_res);
4164  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
4165  (void)attr; /* avoid potential warning */
4166  x86_insn_size_t const size = X86_SIZE_32;
4167  init_ia32_attributes(res, size);
4168  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
4169  out_infos[0].req = &ia32_requirements_gp_esp_I;
4170 
4171  verify_new_node(res);
4172  return optimize_node(res);
4173 }
4174 
4175 ir_node *new_bd_ia32_Ret(dbg_info *dbgi, ir_node *block, int const arity, ir_node *const *const in, arch_register_req_t const **const in_reqs, uint16_t pop)
4176 {
4177 
4178 
4179  ir_graph *const irg = get_irn_irg(block);
4180  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Ret, mode_X, arity, in);
4181 
4182  /* init node attributes */
4183 
4184  /* flags */
4185  arch_irn_flags_t irn_flags = arch_irn_flags_none;
4186  int const n_res = 1;
4187  be_info_init_irn(res, irn_flags, in_reqs, n_res);
4188  ia32_return_attr_t *const attr = (ia32_return_attr_t*)get_irn_generic_attr(res);
4189  (void)attr; /* avoid potential warning */
4190  x86_insn_size_t const size = X86_SIZE_32;
4191  init_ia32_attributes(res, size);
4192  init_ia32_return_attributes(res, pop);
4193  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
4194  out_infos[0].req = &arch_exec_requirement;
4195 
4196  verify_new_node(res);
4197  return optimize_node(res);
4198 }
4199 
4200 ir_node *new_bd_ia32_Rol(dbg_info *dbgi, ir_node *block, ir_node *val, ir_node *count, x86_insn_size_t size)
4201 {
4202  static arch_register_req_t const *in_reqs[] = {
4203  &ia32_class_reg_req_gp,
4204  &ia32_single_reg_req_gp_ecx,
4205  };
4206 
4207  /* construct in array */
4208  ir_node *const in[] = {
4209  val,
4210  count,
4211  };
4212 
4213  ir_graph *const irg = get_irn_irg(block);
4214  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Rol, ia32_mode_gp, 2, in);
4215 
4216  /* init node attributes */
4217 
4218  /* flags */
4219  arch_irn_flags_t irn_flags = arch_irn_flags_none;
4220  irn_flags |= arch_irn_flag_modify_flags;
4221  irn_flags |= arch_irn_flag_rematerializable;
4222  int const n_res = 2;
4223  be_info_init_irn(res, irn_flags, in_reqs, n_res);
4224  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
4225  (void)attr; /* avoid potential warning */
4226  init_ia32_attributes(res, size);
4227  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
4228  out_infos[0].req = &ia32_requirements_gp_in_r0_not_in_r1;
4229  out_infos[1].req = &ia32_class_reg_req_flags;
4230 
4231  verify_new_node(res);
4232  return optimize_node(res);
4233 }
4234 
4235 ir_node *new_bd_ia32_Rol_8bit(dbg_info *dbgi, ir_node *block, ir_node *val, ir_node *count, x86_insn_size_t size)
4236 {
4237  static arch_register_req_t const *in_reqs[] = {
4238  &ia32_requirements_gp_eax_ebx_ecx_edx,
4239  &ia32_single_reg_req_gp_ecx,
4240  };
4241 
4242  /* construct in array */
4243  ir_node *const in[] = {
4244  val,
4245  count,
4246  };
4247 
4248  ir_graph *const irg = get_irn_irg(block);
4249  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Rol, ia32_mode_gp, 2, in);
4250 
4251  /* init node attributes */
4252 
4253  /* flags */
4254  arch_irn_flags_t irn_flags = arch_irn_flags_none;
4255  irn_flags |= arch_irn_flag_modify_flags;
4256  irn_flags |= arch_irn_flag_rematerializable;
4257  int const n_res = 2;
4258  be_info_init_irn(res, irn_flags, in_reqs, n_res);
4259  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
4260  (void)attr; /* avoid potential warning */
4261  init_ia32_attributes(res, size);
4262  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
4263  out_infos[0].req = &ia32_requirements_gp_in_r0_not_in_r1;
4264  out_infos[1].req = &ia32_class_reg_req_flags;
4265 
4266  verify_new_node(res);
4267  return optimize_node(res);
4268 }
4269 
4270 ir_node *new_bd_ia32_RolMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *count, x86_insn_size_t size)
4271 {
4272  static arch_register_req_t const *in_reqs[] = {
4273  &ia32_class_reg_req_gp,
4274  &ia32_class_reg_req_gp,
4275  &arch_memory_requirement,
4276  &ia32_single_reg_req_gp_ecx,
4277  };
4278 
4279  /* construct in array */
4280  ir_node *const in[] = {
4281  base,
4282  index,
4283  mem,
4284  count,
4285  };
4286 
4287  ir_graph *const irg = get_irn_irg(block);
4288  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_RolMem, mode_T, 4, in);
4289 
4290  /* init node attributes */
4291 
4292  /* flags */
4293  arch_irn_flags_t irn_flags = arch_irn_flags_none;
4294  irn_flags |= arch_irn_flag_modify_flags;
4295  irn_flags |= arch_irn_flag_rematerializable;
4296  int const n_res = 3;
4297  be_info_init_irn(res, irn_flags, in_reqs, n_res);
4298  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
4299  (void)attr; /* avoid potential warning */
4300  init_ia32_attributes(res, size);
4301  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
4302  out_infos[0].req = &arch_no_requirement;
4303  out_infos[1].req = &ia32_class_reg_req_flags;
4304  out_infos[2].req = &arch_memory_requirement;
4305 
4306  verify_new_node(res);
4307  return optimize_node(res);
4308 }
4309 
4310 ir_node *new_bd_ia32_Ror(dbg_info *dbgi, ir_node *block, ir_node *val, ir_node *count, x86_insn_size_t size)
4311 {
4312  static arch_register_req_t const *in_reqs[] = {
4313  &ia32_class_reg_req_gp,
4314  &ia32_single_reg_req_gp_ecx,
4315  };
4316 
4317  /* construct in array */
4318  ir_node *const in[] = {
4319  val,
4320  count,
4321  };
4322 
4323  ir_graph *const irg = get_irn_irg(block);
4324  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Ror, ia32_mode_gp, 2, in);
4325 
4326  /* init node attributes */
4327 
4328  /* flags */
4329  arch_irn_flags_t irn_flags = arch_irn_flags_none;
4330  irn_flags |= arch_irn_flag_modify_flags;
4331  irn_flags |= arch_irn_flag_rematerializable;
4332  int const n_res = 2;
4333  be_info_init_irn(res, irn_flags, in_reqs, n_res);
4334  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
4335  (void)attr; /* avoid potential warning */
4336  init_ia32_attributes(res, size);
4337  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
4338  out_infos[0].req = &ia32_requirements_gp_in_r0_not_in_r1;
4339  out_infos[1].req = &ia32_class_reg_req_flags;
4340 
4341  verify_new_node(res);
4342  return optimize_node(res);
4343 }
4344 
4345 ir_node *new_bd_ia32_Ror_8bit(dbg_info *dbgi, ir_node *block, ir_node *val, ir_node *count, x86_insn_size_t size)
4346 {
4347  static arch_register_req_t const *in_reqs[] = {
4348  &ia32_requirements_gp_eax_ebx_ecx_edx,
4349  &ia32_single_reg_req_gp_ecx,
4350  };
4351 
4352  /* construct in array */
4353  ir_node *const in[] = {
4354  val,
4355  count,
4356  };
4357 
4358  ir_graph *const irg = get_irn_irg(block);
4359  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Ror, ia32_mode_gp, 2, in);
4360 
4361  /* init node attributes */
4362 
4363  /* flags */
4364  arch_irn_flags_t irn_flags = arch_irn_flags_none;
4365  irn_flags |= arch_irn_flag_modify_flags;
4366  irn_flags |= arch_irn_flag_rematerializable;
4367  int const n_res = 2;
4368  be_info_init_irn(res, irn_flags, in_reqs, n_res);
4369  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
4370  (void)attr; /* avoid potential warning */
4371  init_ia32_attributes(res, size);
4372  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
4373  out_infos[0].req = &ia32_requirements_gp_in_r0_not_in_r1;
4374  out_infos[1].req = &ia32_class_reg_req_flags;
4375 
4376  verify_new_node(res);
4377  return optimize_node(res);
4378 }
4379 
4380 ir_node *new_bd_ia32_RorMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *count, x86_insn_size_t size)
4381 {
4382  static arch_register_req_t const *in_reqs[] = {
4383  &ia32_class_reg_req_gp,
4384  &ia32_class_reg_req_gp,
4385  &arch_memory_requirement,
4386  &ia32_single_reg_req_gp_ecx,
4387  };
4388 
4389  /* construct in array */
4390  ir_node *const in[] = {
4391  base,
4392  index,
4393  mem,
4394  count,
4395  };
4396 
4397  ir_graph *const irg = get_irn_irg(block);
4398  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_RorMem, mode_T, 4, in);
4399 
4400  /* init node attributes */
4401 
4402  /* flags */
4403  arch_irn_flags_t irn_flags = arch_irn_flags_none;
4404  irn_flags |= arch_irn_flag_modify_flags;
4405  irn_flags |= arch_irn_flag_rematerializable;
4406  int const n_res = 3;
4407  be_info_init_irn(res, irn_flags, in_reqs, n_res);
4408  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
4409  (void)attr; /* avoid potential warning */
4410  init_ia32_attributes(res, size);
4411  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
4412  out_infos[0].req = &arch_no_requirement;
4413  out_infos[1].req = &ia32_class_reg_req_flags;
4414  out_infos[2].req = &arch_memory_requirement;
4415 
4416  verify_new_node(res);
4417  return optimize_node(res);
4418 }
4419 
4420 ir_node *new_bd_ia32_Sahf(dbg_info *dbgi, ir_node *block, ir_node *val)
4421 {
4422  static arch_register_req_t const *in_reqs[] = {
4423  &ia32_single_reg_req_gp_eax,
4424  };
4425 
4426  /* construct in array */
4427  ir_node *const in[] = {
4428  val,
4429  };
4430 
4431  ir_graph *const irg = get_irn_irg(block);
4432  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Sahf, ia32_mode_flags, 1, in);
4433 
4434  /* init node attributes */
4435 
4436  /* flags */
4437  arch_irn_flags_t irn_flags = arch_irn_flags_none;
4438  irn_flags |= arch_irn_flag_rematerializable;
4439  int const n_res = 1;
4440  be_info_init_irn(res, irn_flags, in_reqs, n_res);
4441  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
4442  (void)attr; /* avoid potential warning */
4443  x86_insn_size_t const size = X86_SIZE_16;
4444  init_ia32_attributes(res, size);
4445  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
4446  out_infos[0].req = &ia32_class_reg_req_flags;
4447 
4448  verify_new_node(res);
4449  return optimize_node(res);
4450 }
4451 
4452 ir_node *new_bd_ia32_Sar(dbg_info *dbgi, ir_node *block, ir_node *val, ir_node *count, x86_insn_size_t size)
4453 {
4454  static arch_register_req_t const *in_reqs[] = {
4455  &ia32_class_reg_req_gp,
4456  &ia32_single_reg_req_gp_ecx,
4457  };
4458 
4459  /* construct in array */
4460  ir_node *const in[] = {
4461  val,
4462  count,
4463  };
4464 
4465  ir_graph *const irg = get_irn_irg(block);
4466  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Sar, ia32_mode_gp, 2, in);
4467 
4468  /* init node attributes */
4469 
4470  /* flags */
4471  arch_irn_flags_t irn_flags = arch_irn_flags_none;
4472  irn_flags |= arch_irn_flag_modify_flags;
4473  irn_flags |= arch_irn_flag_rematerializable;
4474  int const n_res = 2;
4475  be_info_init_irn(res, irn_flags, in_reqs, n_res);
4476  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
4477  (void)attr; /* avoid potential warning */
4478  init_ia32_attributes(res, size);
4479  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
4480  out_infos[0].req = &ia32_requirements_gp_in_r0_not_in_r1;
4481  out_infos[1].req = &ia32_class_reg_req_flags;
4482 
4483  verify_new_node(res);
4484  return optimize_node(res);
4485 }
4486 
4487 ir_node *new_bd_ia32_Sar_8bit(dbg_info *dbgi, ir_node *block, ir_node *val, ir_node *count, x86_insn_size_t size)
4488 {
4489  static arch_register_req_t const *in_reqs[] = {
4490  &ia32_requirements_gp_eax_ebx_ecx_edx,
4491  &ia32_single_reg_req_gp_ecx,
4492  };
4493 
4494  /* construct in array */
4495  ir_node *const in[] = {
4496  val,
4497  count,
4498  };
4499 
4500  ir_graph *const irg = get_irn_irg(block);
4501  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Sar, ia32_mode_gp, 2, in);
4502 
4503  /* init node attributes */
4504 
4505  /* flags */
4506  arch_irn_flags_t irn_flags = arch_irn_flags_none;
4507  irn_flags |= arch_irn_flag_modify_flags;
4508  irn_flags |= arch_irn_flag_rematerializable;
4509  int const n_res = 2;
4510  be_info_init_irn(res, irn_flags, in_reqs, n_res);
4511  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
4512  (void)attr; /* avoid potential warning */
4513  init_ia32_attributes(res, size);
4514  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
4515  out_infos[0].req = &ia32_requirements_gp_in_r0_not_in_r1;
4516  out_infos[1].req = &ia32_class_reg_req_flags;
4517 
4518  verify_new_node(res);
4519  return optimize_node(res);
4520 }
4521 
4522 ir_node *new_bd_ia32_SarMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *count, x86_insn_size_t size)
4523 {
4524  static arch_register_req_t const *in_reqs[] = {
4525  &ia32_class_reg_req_gp,
4526  &ia32_class_reg_req_gp,
4527  &arch_memory_requirement,
4528  &ia32_single_reg_req_gp_ecx,
4529  };
4530 
4531  /* construct in array */
4532  ir_node *const in[] = {
4533  base,
4534  index,
4535  mem,
4536  count,
4537  };
4538 
4539  ir_graph *const irg = get_irn_irg(block);
4540  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_SarMem, mode_T, 4, in);
4541 
4542  /* init node attributes */
4543 
4544  /* flags */
4545  arch_irn_flags_t irn_flags = arch_irn_flags_none;
4546  irn_flags |= arch_irn_flag_modify_flags;
4547  irn_flags |= arch_irn_flag_rematerializable;
4548  int const n_res = 3;
4549  be_info_init_irn(res, irn_flags, in_reqs, n_res);
4550  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
4551  (void)attr; /* avoid potential warning */
4552  init_ia32_attributes(res, size);
4553  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
4554  out_infos[0].req = &arch_no_requirement;
4555  out_infos[1].req = &ia32_class_reg_req_flags;
4556  out_infos[2].req = &arch_memory_requirement;
4557 
4558  verify_new_node(res);
4559  return optimize_node(res);
4560 }
4561 
4562 ir_node *new_bd_ia32_Sbb(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *minuend, ir_node *subtrahend, ir_node *eflags, x86_insn_size_t size)
4563 {
4564  static arch_register_req_t const *in_reqs[] = {
4565  &ia32_class_reg_req_gp,
4566  &ia32_class_reg_req_gp,
4567  &arch_memory_requirement,
4568  &ia32_class_reg_req_gp,
4569  &ia32_class_reg_req_gp,
4570  &ia32_class_reg_req_flags,
4571  };
4572 
4573  /* construct in array */
4574  ir_node *const in[] = {
4575  base,
4576  index,
4577  mem,
4578  minuend,
4579  subtrahend,
4580  eflags,
4581  };
4582 
4583  ir_graph *const irg = get_irn_irg(block);
4584  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Sbb, ia32_mode_gp, 6, in);
4585 
4586  /* init node attributes */
4587 
4588  /* flags */
4589  arch_irn_flags_t irn_flags = arch_irn_flags_none;
4590  irn_flags |= arch_irn_flag_modify_flags;
4591  int const n_res = 3;
4592  be_info_init_irn(res, irn_flags, in_reqs, n_res);
4593  ia32_condcode_attr_t *const attr = (ia32_condcode_attr_t*)get_irn_generic_attr(res);
4594  (void)attr; /* avoid potential warning */
4595  x86_condition_code_t condition_code = x86_cc_carry;
4596  init_ia32_attributes(res, size);
4597  init_ia32_condcode_attributes(res, condition_code);
4598  set_ia32_am_support(res, ia32_am_binary);
4599  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
4600  out_infos[0].req = &ia32_requirements_gp_in_r3;
4601  out_infos[1].req = &ia32_class_reg_req_flags;
4602  out_infos[2].req = &arch_memory_requirement;
4603 
4604  verify_new_node(res);
4605  return optimize_node(res);
4606 }
4607 
4608 ir_node *new_bd_ia32_Sbb0(dbg_info *dbgi, ir_node *block, ir_node *op0, x86_insn_size_t size)
4609 {
4610  static arch_register_req_t const *in_reqs[] = {
4611  &ia32_class_reg_req_flags,
4612  };
4613 
4614  /* construct in array */
4615  ir_node *const in[] = {
4616  op0,
4617  };
4618 
4619  ir_graph *const irg = get_irn_irg(block);
4620  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Sbb0, ia32_mode_gp, 1, in);
4621 
4622  /* init node attributes */
4623 
4624  /* flags */
4625  arch_irn_flags_t irn_flags = arch_irn_flags_none;
4626  irn_flags |= arch_irn_flag_modify_flags;
4627  int const n_res = 2;
4628  be_info_init_irn(res, irn_flags, in_reqs, n_res);
4629  ia32_condcode_attr_t *const attr = (ia32_condcode_attr_t*)get_irn_generic_attr(res);
4630  (void)attr; /* avoid potential warning */
4631  x86_condition_code_t condition_code = x86_cc_carry;
4632  init_ia32_attributes(res, size);
4633  init_ia32_condcode_attributes(res, condition_code);
4634  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
4635  out_infos[0].req = &ia32_class_reg_req_gp;
4636  out_infos[1].req = &ia32_class_reg_req_flags;
4637 
4638  verify_new_node(res);
4639  return optimize_node(res);
4640 }
4641 
4642 ir_node *new_bd_ia32_Setcc(dbg_info *dbgi, ir_node *block, ir_node *eflags, x86_condition_code_t condition_code)
4643 {
4644  static arch_register_req_t const *in_reqs[] = {
4645  &ia32_class_reg_req_flags,
4646  };
4647 
4648  /* construct in array */
4649  ir_node *const in[] = {
4650  eflags,
4651  };
4652 
4653  ir_graph *const irg = get_irn_irg(block);
4654  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Setcc, ia32_mode_gp, 1, in);
4655 
4656  /* init node attributes */
4657 
4658  /* flags */
4659  arch_irn_flags_t irn_flags = arch_irn_flags_none;
4660  int const n_res = 1;
4661  be_info_init_irn(res, irn_flags, in_reqs, n_res);
4662  ia32_condcode_attr_t *const attr = (ia32_condcode_attr_t*)get_irn_generic_attr(res);
4663  (void)attr; /* avoid potential warning */
4664  x86_insn_size_t const size = X86_SIZE_8;
4665  init_ia32_attributes(res, size);
4666  init_ia32_condcode_attributes(res, condition_code);
4667  if (condition_code & x86_cc_additional_float_cases) {
4668  arch_add_irn_flags(res, arch_irn_flag_modify_flags);
4669  /* attr->latency = 3; */
4670  }
4671 
4672  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
4673  out_infos[0].req = &ia32_requirements_gp_eax_ebx_ecx_edx;
4674 
4675  verify_new_node(res);
4676  return optimize_node(res);
4677 }
4678 
4679 ir_node *new_bd_ia32_SetccMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *eflags, x86_condition_code_t condition_code)
4680 {
4681  static arch_register_req_t const *in_reqs[] = {
4682  &ia32_class_reg_req_gp,
4683  &ia32_class_reg_req_gp,
4684  &arch_memory_requirement,
4685  &ia32_class_reg_req_flags,
4686  };
4687 
4688  /* construct in array */
4689  ir_node *const in[] = {
4690  base,
4691  index,
4692  mem,
4693  eflags,
4694  };
4695 
4696  ir_graph *const irg = get_irn_irg(block);
4697  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_SetccMem, mode_M, 4, in);
4698 
4699  /* init node attributes */
4700 
4701  /* flags */
4702  arch_irn_flags_t irn_flags = arch_irn_flags_none;
4703  int const n_res = 1;
4704  be_info_init_irn(res, irn_flags, in_reqs, n_res);
4705  ia32_condcode_attr_t *const attr = (ia32_condcode_attr_t*)get_irn_generic_attr(res);
4706  (void)attr; /* avoid potential warning */
4707  x86_insn_size_t const size = X86_SIZE_8;
4708  init_ia32_attributes(res, size);
4709  init_ia32_condcode_attributes(res, condition_code);
4710  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
4711  out_infos[0].req = &arch_memory_requirement;
4712 
4713  verify_new_node(res);
4714  return optimize_node(res);
4715 }
4716 
4717 ir_node *new_bd_ia32_Shl(dbg_info *dbgi, ir_node *block, ir_node *val, ir_node *count, x86_insn_size_t size)
4718 {
4719  static arch_register_req_t const *in_reqs[] = {
4720  &ia32_class_reg_req_gp,
4721  &ia32_single_reg_req_gp_ecx,
4722  };
4723 
4724  /* construct in array */
4725  ir_node *const in[] = {
4726  val,
4727  count,
4728  };
4729 
4730  ir_graph *const irg = get_irn_irg(block);
4731  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Shl, ia32_mode_gp, 2, in);
4732 
4733  /* init node attributes */
4734 
4735  /* flags */
4736  arch_irn_flags_t irn_flags = arch_irn_flags_none;
4737  irn_flags |= arch_irn_flag_modify_flags;
4738  irn_flags |= arch_irn_flag_rematerializable;
4739  int const n_res = 2;
4740  be_info_init_irn(res, irn_flags, in_reqs, n_res);
4741  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
4742  (void)attr; /* avoid potential warning */
4743  init_ia32_attributes(res, size);
4744  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
4745  out_infos[0].req = &ia32_requirements_gp_in_r0_not_in_r1;
4746  out_infos[1].req = &ia32_class_reg_req_flags;
4747 
4748  verify_new_node(res);
4749  return optimize_node(res);
4750 }
4751 
4752 ir_node *new_bd_ia32_Shl_8bit(dbg_info *dbgi, ir_node *block, ir_node *val, ir_node *count, x86_insn_size_t size)
4753 {
4754  static arch_register_req_t const *in_reqs[] = {
4755  &ia32_requirements_gp_eax_ebx_ecx_edx,
4756  &ia32_single_reg_req_gp_ecx,
4757  };
4758 
4759  /* construct in array */
4760  ir_node *const in[] = {
4761  val,
4762  count,
4763  };
4764 
4765  ir_graph *const irg = get_irn_irg(block);
4766  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Shl, ia32_mode_gp, 2, in);
4767 
4768  /* init node attributes */
4769 
4770  /* flags */
4771  arch_irn_flags_t irn_flags = arch_irn_flags_none;
4772  irn_flags |= arch_irn_flag_modify_flags;
4773  irn_flags |= arch_irn_flag_rematerializable;
4774  int const n_res = 2;
4775  be_info_init_irn(res, irn_flags, in_reqs, n_res);
4776  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
4777  (void)attr; /* avoid potential warning */
4778  init_ia32_attributes(res, size);
4779  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
4780  out_infos[0].req = &ia32_requirements_gp_in_r0_not_in_r1;
4781  out_infos[1].req = &ia32_class_reg_req_flags;
4782 
4783  verify_new_node(res);
4784  return optimize_node(res);
4785 }
4786 
4787 ir_node *new_bd_ia32_ShlD(dbg_info *dbgi, ir_node *block, ir_node *val_high, ir_node *val_low, ir_node *count)
4788 {
4789  static arch_register_req_t const *in_reqs[] = {
4790  &ia32_class_reg_req_gp,
4791  &ia32_class_reg_req_gp,
4792  &ia32_single_reg_req_gp_ecx,
4793  };
4794 
4795  /* construct in array */
4796  ir_node *const in[] = {
4797  val_high,
4798  val_low,
4799  count,
4800  };
4801 
4802  ir_graph *const irg = get_irn_irg(block);
4803  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_ShlD, ia32_mode_gp, 3, in);
4804 
4805  /* init node attributes */
4806 
4807  /* flags */
4808  arch_irn_flags_t irn_flags = arch_irn_flags_none;
4809  irn_flags |= arch_irn_flag_modify_flags;
4810  irn_flags |= arch_irn_flag_rematerializable;
4811  int const n_res = 2;
4812  be_info_init_irn(res, irn_flags, in_reqs, n_res);
4813  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
4814  (void)attr; /* avoid potential warning */
4815  x86_insn_size_t const size = X86_SIZE_32;
4816  init_ia32_attributes(res, size);
4817  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
4818  out_infos[0].req = &ia32_requirements_gp_in_r0_not_in_r1_not_in_r2;
4819  out_infos[1].req = &ia32_class_reg_req_flags;
4820 
4821  verify_new_node(res);
4822  return optimize_node(res);
4823 }
4824 
4825 ir_node *new_bd_ia32_ShlD_imm(dbg_info *dbgi, ir_node *block, ir_node *val_high, ir_node *val_low, ir_node *count)
4826 {
4827  static arch_register_req_t const *in_reqs[] = {
4828  &ia32_class_reg_req_gp,
4829  &ia32_class_reg_req_gp,
4830  &ia32_single_reg_req_gp_ecx,
4831  };
4832 
4833  /* construct in array */
4834  ir_node *const in[] = {
4835  val_high,
4836  val_low,
4837  count,
4838  };
4839 
4840  ir_graph *const irg = get_irn_irg(block);
4841  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_ShlD, ia32_mode_gp, 3, in);
4842 
4843  /* init node attributes */
4844 
4845  /* flags */
4846  arch_irn_flags_t irn_flags = arch_irn_flags_none;
4847  irn_flags |= arch_irn_flag_modify_flags;
4848  irn_flags |= arch_irn_flag_rematerializable;
4849  int const n_res = 2;
4850  be_info_init_irn(res, irn_flags, in_reqs, n_res);
4851  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
4852  (void)attr; /* avoid potential warning */
4853  x86_insn_size_t const size = X86_SIZE_32;
4854  init_ia32_attributes(res, size);
4855  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
4856  out_infos[0].req = &ia32_requirements_gp_in_r0_in_r1;
4857  out_infos[1].req = &ia32_class_reg_req_flags;
4858 
4859  verify_new_node(res);
4860  return optimize_node(res);
4861 }
4862 
4863 ir_node *new_bd_ia32_ShlMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *count, x86_insn_size_t size)
4864 {
4865  static arch_register_req_t const *in_reqs[] = {
4866  &ia32_class_reg_req_gp,
4867  &ia32_class_reg_req_gp,
4868  &arch_memory_requirement,
4869  &ia32_single_reg_req_gp_ecx,
4870  };
4871 
4872  /* construct in array */
4873  ir_node *const in[] = {
4874  base,
4875  index,
4876  mem,
4877  count,
4878  };
4879 
4880  ir_graph *const irg = get_irn_irg(block);
4881  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_ShlMem, mode_T, 4, in);
4882 
4883  /* init node attributes */
4884 
4885  /* flags */
4886  arch_irn_flags_t irn_flags = arch_irn_flags_none;
4887  irn_flags |= arch_irn_flag_modify_flags;
4888  irn_flags |= arch_irn_flag_rematerializable;
4889  int const n_res = 3;
4890  be_info_init_irn(res, irn_flags, in_reqs, n_res);
4891  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
4892  (void)attr; /* avoid potential warning */
4893  init_ia32_attributes(res, size);
4894  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
4895  out_infos[0].req = &arch_no_requirement;
4896  out_infos[1].req = &ia32_class_reg_req_flags;
4897  out_infos[2].req = &arch_memory_requirement;
4898 
4899  verify_new_node(res);
4900  return optimize_node(res);
4901 }
4902 
4903 ir_node *new_bd_ia32_Shr(dbg_info *dbgi, ir_node *block, ir_node *val, ir_node *count, x86_insn_size_t size)
4904 {
4905  static arch_register_req_t const *in_reqs[] = {
4906  &ia32_class_reg_req_gp,
4907  &ia32_single_reg_req_gp_ecx,
4908  };
4909 
4910  /* construct in array */
4911  ir_node *const in[] = {
4912  val,
4913  count,
4914  };
4915 
4916  ir_graph *const irg = get_irn_irg(block);
4917  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Shr, ia32_mode_gp, 2, in);
4918 
4919  /* init node attributes */
4920 
4921  /* flags */
4922  arch_irn_flags_t irn_flags = arch_irn_flags_none;
4923  irn_flags |= arch_irn_flag_modify_flags;
4924  irn_flags |= arch_irn_flag_rematerializable;
4925  int const n_res = 2;
4926  be_info_init_irn(res, irn_flags, in_reqs, n_res);
4927  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
4928  (void)attr; /* avoid potential warning */
4929  init_ia32_attributes(res, size);
4930  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
4931  out_infos[0].req = &ia32_requirements_gp_in_r0_not_in_r1;
4932  out_infos[1].req = &ia32_class_reg_req_flags;
4933 
4934  verify_new_node(res);
4935  return optimize_node(res);
4936 }
4937 
4938 ir_node *new_bd_ia32_Shr_8bit(dbg_info *dbgi, ir_node *block, ir_node *val, ir_node *count, x86_insn_size_t size)
4939 {
4940  static arch_register_req_t const *in_reqs[] = {
4941  &ia32_requirements_gp_eax_ebx_ecx_edx,
4942  &ia32_single_reg_req_gp_ecx,
4943  };
4944 
4945  /* construct in array */
4946  ir_node *const in[] = {
4947  val,
4948  count,
4949  };
4950 
4951  ir_graph *const irg = get_irn_irg(block);
4952  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Shr, ia32_mode_gp, 2, in);
4953 
4954  /* init node attributes */
4955 
4956  /* flags */
4957  arch_irn_flags_t irn_flags = arch_irn_flags_none;
4958  irn_flags |= arch_irn_flag_modify_flags;
4959  irn_flags |= arch_irn_flag_rematerializable;
4960  int const n_res = 2;
4961  be_info_init_irn(res, irn_flags, in_reqs, n_res);
4962  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
4963  (void)attr; /* avoid potential warning */
4964  init_ia32_attributes(res, size);
4965  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
4966  out_infos[0].req = &ia32_requirements_gp_in_r0_not_in_r1;
4967  out_infos[1].req = &ia32_class_reg_req_flags;
4968 
4969  verify_new_node(res);
4970  return optimize_node(res);
4971 }
4972 
4973 ir_node *new_bd_ia32_ShrD(dbg_info *dbgi, ir_node *block, ir_node *val_high, ir_node *val_low, ir_node *count)
4974 {
4975  static arch_register_req_t const *in_reqs[] = {
4976  &ia32_class_reg_req_gp,
4977  &ia32_class_reg_req_gp,
4978  &ia32_single_reg_req_gp_ecx,
4979  };
4980 
4981  /* construct in array */
4982  ir_node *const in[] = {
4983  val_high,
4984  val_low,
4985  count,
4986  };
4987 
4988  ir_graph *const irg = get_irn_irg(block);
4989  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_ShrD, ia32_mode_gp, 3, in);
4990 
4991  /* init node attributes */
4992 
4993  /* flags */
4994  arch_irn_flags_t irn_flags = arch_irn_flags_none;
4995  irn_flags |= arch_irn_flag_modify_flags;
4996  irn_flags |= arch_irn_flag_rematerializable;
4997  int const n_res = 2;
4998  be_info_init_irn(res, irn_flags, in_reqs, n_res);
4999  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
5000  (void)attr; /* avoid potential warning */
5001  x86_insn_size_t const size = X86_SIZE_32;
5002  init_ia32_attributes(res, size);
5003  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
5004  out_infos[0].req = &ia32_requirements_gp_in_r0_not_in_r1_not_in_r2;
5005  out_infos[1].req = &ia32_class_reg_req_flags;
5006 
5007  verify_new_node(res);
5008  return optimize_node(res);
5009 }
5010 
5011 ir_node *new_bd_ia32_ShrD_imm(dbg_info *dbgi, ir_node *block, ir_node *val_high, ir_node *val_low, ir_node *count)
5012 {
5013  static arch_register_req_t const *in_reqs[] = {
5014  &ia32_class_reg_req_gp,
5015  &ia32_class_reg_req_gp,
5016  &ia32_single_reg_req_gp_ecx,
5017  };
5018 
5019  /* construct in array */
5020  ir_node *const in[] = {
5021  val_high,
5022  val_low,
5023  count,
5024  };
5025 
5026  ir_graph *const irg = get_irn_irg(block);
5027  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_ShrD, ia32_mode_gp, 3, in);
5028 
5029  /* init node attributes */
5030 
5031  /* flags */
5032  arch_irn_flags_t irn_flags = arch_irn_flags_none;
5033  irn_flags |= arch_irn_flag_modify_flags;
5034  irn_flags |= arch_irn_flag_rematerializable;
5035  int const n_res = 2;
5036  be_info_init_irn(res, irn_flags, in_reqs, n_res);
5037  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
5038  (void)attr; /* avoid potential warning */
5039  x86_insn_size_t const size = X86_SIZE_32;
5040  init_ia32_attributes(res, size);
5041  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
5042  out_infos[0].req = &ia32_requirements_gp_in_r0_in_r1;
5043  out_infos[1].req = &ia32_class_reg_req_flags;
5044 
5045  verify_new_node(res);
5046  return optimize_node(res);
5047 }
5048 
5049 ir_node *new_bd_ia32_ShrMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *count, x86_insn_size_t size)
5050 {
5051  static arch_register_req_t const *in_reqs[] = {
5052  &ia32_class_reg_req_gp,
5053  &ia32_class_reg_req_gp,
5054  &arch_memory_requirement,
5055  &ia32_single_reg_req_gp_ecx,
5056  };
5057 
5058  /* construct in array */
5059  ir_node *const in[] = {
5060  base,
5061  index,
5062  mem,
5063  count,
5064  };
5065 
5066  ir_graph *const irg = get_irn_irg(block);
5067  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_ShrMem, mode_T, 4, in);
5068 
5069  /* init node attributes */
5070 
5071  /* flags */
5072  arch_irn_flags_t irn_flags = arch_irn_flags_none;
5073  irn_flags |= arch_irn_flag_modify_flags;
5074  irn_flags |= arch_irn_flag_rematerializable;
5075  int const n_res = 3;
5076  be_info_init_irn(res, irn_flags, in_reqs, n_res);
5077  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
5078  (void)attr; /* avoid potential warning */
5079  init_ia32_attributes(res, size);
5080  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
5081  out_infos[0].req = &arch_no_requirement;
5082  out_infos[1].req = &ia32_class_reg_req_flags;
5083  out_infos[2].req = &arch_memory_requirement;
5084 
5085  verify_new_node(res);
5086  return optimize_node(res);
5087 }
5088 
5089 ir_node *new_bd_ia32_Stc(dbg_info *dbgi, ir_node *block)
5090 {
5091  arch_register_req_t const **const in_reqs = NULL;
5092 
5093 
5094  ir_graph *const irg = get_irn_irg(block);
5095  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Stc, ia32_mode_flags, 0, NULL);
5096 
5097  /* init node attributes */
5098 
5099  /* flags */
5100  arch_irn_flags_t irn_flags = arch_irn_flags_none;
5101  irn_flags |= arch_irn_flag_modify_flags;
5102  irn_flags |= arch_irn_flag_rematerializable;
5103  int const n_res = 1;
5104  be_info_init_irn(res, irn_flags, in_reqs, n_res);
5105  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
5106  (void)attr; /* avoid potential warning */
5107  x86_insn_size_t const size = X86_SIZE_32;
5108  init_ia32_attributes(res, size);
5109  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
5110  out_infos[0].req = &ia32_class_reg_req_flags;
5111 
5112  verify_new_node(res);
5113  return optimize_node(res);
5114 }
5115 
5116 ir_node *new_bd_ia32_Store(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size)
5117 {
5118  static arch_register_req_t const *in_reqs[] = {
5119  &ia32_class_reg_req_gp,
5120  &ia32_class_reg_req_gp,
5121  &arch_memory_requirement,
5122  &ia32_class_reg_req_gp,
5123  };
5124 
5125  /* construct in array */
5126  ir_node *const in[] = {
5127  base,
5128  index,
5129  mem,
5130  val,
5131  };
5132 
5133  ir_graph *const irg = get_irn_irg(block);
5134  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Store, mode_T, 4, in);
5135 
5136  /* init node attributes */
5137 
5138  /* flags */
5139  arch_irn_flags_t irn_flags = arch_irn_flags_none;
5140  int const n_res = 3;
5141  be_info_init_irn(res, irn_flags, in_reqs, n_res);
5142  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
5143  (void)attr; /* avoid potential warning */
5144  init_ia32_attributes(res, size);
5145  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
5146  out_infos[0].req = &arch_memory_requirement;
5147  out_infos[1].req = &arch_exec_requirement;
5148  out_infos[2].req = &arch_exec_requirement;
5149 
5150  verify_new_node(res);
5151  return optimize_node(res);
5152 }
5153 
5154 ir_node *new_bd_ia32_Store_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size)
5155 {
5156  static arch_register_req_t const *in_reqs[] = {
5157  &ia32_class_reg_req_gp,
5158  &ia32_class_reg_req_gp,
5159  &arch_memory_requirement,
5160  &ia32_requirements_gp_eax_ebx_ecx_edx,
5161  };
5162 
5163  /* construct in array */
5164  ir_node *const in[] = {
5165  base,
5166  index,
5167  mem,
5168  val,
5169  };
5170 
5171  ir_graph *const irg = get_irn_irg(block);
5172  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Store, mode_T, 4, in);
5173 
5174  /* init node attributes */
5175 
5176  /* flags */
5177  arch_irn_flags_t irn_flags = arch_irn_flags_none;
5178  int const n_res = 3;
5179  be_info_init_irn(res, irn_flags, in_reqs, n_res);
5180  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
5181  (void)attr; /* avoid potential warning */
5182  init_ia32_attributes(res, size);
5183  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
5184  out_infos[0].req = &arch_memory_requirement;
5185  out_infos[1].req = &arch_exec_requirement;
5186  out_infos[2].req = &arch_exec_requirement;
5187 
5188  verify_new_node(res);
5189  return optimize_node(res);
5190 }
5191 
5192 ir_node *new_bd_ia32_Sub(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *minuend, ir_node *subtrahend, x86_insn_size_t size)
5193 {
5194  static arch_register_req_t const *in_reqs[] = {
5195  &ia32_class_reg_req_gp,
5196  &ia32_class_reg_req_gp,
5197  &arch_memory_requirement,
5198  &ia32_class_reg_req_gp,
5199  &ia32_class_reg_req_gp,
5200  };
5201 
5202  /* construct in array */
5203  ir_node *const in[] = {
5204  base,
5205  index,
5206  mem,
5207  minuend,
5208  subtrahend,
5209  };
5210 
5211  ir_graph *const irg = get_irn_irg(block);
5212  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Sub, ia32_mode_gp, 5, in);
5213 
5214  /* init node attributes */
5215 
5216  /* flags */
5217  arch_irn_flags_t irn_flags = arch_irn_flags_none;
5218  irn_flags |= arch_irn_flag_modify_flags;
5219  irn_flags |= arch_irn_flag_rematerializable;
5220  int const n_res = 3;
5221  be_info_init_irn(res, irn_flags, in_reqs, n_res);
5222  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
5223  (void)attr; /* avoid potential warning */
5224  init_ia32_attributes(res, size);
5225  set_ia32_am_support(res, ia32_am_binary);
5226  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
5227  out_infos[0].req = &ia32_requirements_gp_in_r3;
5228  out_infos[1].req = &ia32_class_reg_req_flags;
5229  out_infos[2].req = &arch_memory_requirement;
5230 
5231  verify_new_node(res);
5232  return optimize_node(res);
5233 }
5234 
5235 ir_node *new_bd_ia32_Sub_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *minuend, ir_node *subtrahend, x86_insn_size_t size)
5236 {
5237  static arch_register_req_t const *in_reqs[] = {
5238  &ia32_class_reg_req_gp,
5239  &ia32_class_reg_req_gp,
5240  &arch_memory_requirement,
5241  &ia32_requirements_gp_eax_ebx_ecx_edx,
5242  &ia32_requirements_gp_eax_ebx_ecx_edx,
5243  };
5244 
5245  /* construct in array */
5246  ir_node *const in[] = {
5247  base,
5248  index,
5249  mem,
5250  minuend,
5251  subtrahend,
5252  };
5253 
5254  ir_graph *const irg = get_irn_irg(block);
5255  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Sub, ia32_mode_gp, 5, in);
5256 
5257  /* init node attributes */
5258 
5259  /* flags */
5260  arch_irn_flags_t irn_flags = arch_irn_flags_none;
5261  irn_flags |= arch_irn_flag_modify_flags;
5262  irn_flags |= arch_irn_flag_rematerializable;
5263  int const n_res = 3;
5264  be_info_init_irn(res, irn_flags, in_reqs, n_res);
5265  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
5266  (void)attr; /* avoid potential warning */
5267  init_ia32_attributes(res, size);
5268  set_ia32_am_support(res, ia32_am_binary);
5269  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
5270  out_infos[0].req = &ia32_requirements_gp_eax_ebx_ecx_edx_in_r3;
5271  out_infos[1].req = &ia32_class_reg_req_flags;
5272  out_infos[2].req = &arch_memory_requirement;
5273 
5274  verify_new_node(res);
5275  return optimize_node(res);
5276 }
5277 
5278 ir_node *new_bd_ia32_SubMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size)
5279 {
5280  static arch_register_req_t const *in_reqs[] = {
5281  &ia32_class_reg_req_gp,
5282  &ia32_class_reg_req_gp,
5283  &arch_memory_requirement,
5284  &ia32_class_reg_req_gp,
5285  };
5286 
5287  /* construct in array */
5288  ir_node *const in[] = {
5289  base,
5290  index,
5291  mem,
5292  val,
5293  };
5294 
5295  ir_graph *const irg = get_irn_irg(block);
5296  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_SubMem, mode_T, 4, in);
5297 
5298  /* init node attributes */
5299 
5300  /* flags */
5301  arch_irn_flags_t irn_flags = arch_irn_flags_none;
5302  irn_flags |= arch_irn_flag_modify_flags;
5303  irn_flags |= arch_irn_flag_rematerializable;
5304  int const n_res = 3;
5305  be_info_init_irn(res, irn_flags, in_reqs, n_res);
5306  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
5307  (void)attr; /* avoid potential warning */
5308  init_ia32_attributes(res, size);
5309  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
5310  out_infos[0].req = &arch_no_requirement;
5311  out_infos[1].req = &ia32_class_reg_req_flags;
5312  out_infos[2].req = &arch_memory_requirement;
5313 
5314  verify_new_node(res);
5315  return optimize_node(res);
5316 }
5317 
5318 ir_node *new_bd_ia32_SubMem_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size)
5319 {
5320  static arch_register_req_t const *in_reqs[] = {
5321  &ia32_class_reg_req_gp,
5322  &ia32_class_reg_req_gp,
5323  &arch_memory_requirement,
5324  &ia32_requirements_gp_eax_ebx_ecx_edx,
5325  };
5326 
5327  /* construct in array */
5328  ir_node *const in[] = {
5329  base,
5330  index,
5331  mem,
5332  val,
5333  };
5334 
5335  ir_graph *const irg = get_irn_irg(block);
5336  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_SubMem, mode_T, 4, in);
5337 
5338  /* init node attributes */
5339 
5340  /* flags */
5341  arch_irn_flags_t irn_flags = arch_irn_flags_none;
5342  irn_flags |= arch_irn_flag_modify_flags;
5343  irn_flags |= arch_irn_flag_rematerializable;
5344  int const n_res = 3;
5345  be_info_init_irn(res, irn_flags, in_reqs, n_res);
5346  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
5347  (void)attr; /* avoid potential warning */
5348  init_ia32_attributes(res, size);
5349  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
5350  out_infos[0].req = &arch_no_requirement;
5351  out_infos[1].req = &ia32_class_reg_req_flags;
5352  out_infos[2].req = &arch_memory_requirement;
5353 
5354  verify_new_node(res);
5355  return optimize_node(res);
5356 }
5357 
5358 ir_node *new_bd_ia32_SubSP(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *stack, ir_node *amount)
5359 {
5360  static arch_register_req_t const *in_reqs[] = {
5361  &ia32_class_reg_req_gp,
5362  &ia32_class_reg_req_gp,
5363  &arch_memory_requirement,
5364  &ia32_single_reg_req_gp_esp,
5365  &ia32_class_reg_req_gp,
5366  };
5367 
5368  /* construct in array */
5369  ir_node *const in[] = {
5370  base,
5371  index,
5372  mem,
5373  stack,
5374  amount,
5375  };
5376 
5377  ir_graph *const irg = get_irn_irg(block);
5378  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_SubSP, mode_T, 5, in);
5379 
5380  /* init node attributes */
5381 
5382  /* flags */
5383  arch_irn_flags_t irn_flags = arch_irn_flags_none;
5384  irn_flags |= arch_irn_flag_modify_flags;
5385  int const n_res = 3;
5386  be_info_init_irn(res, irn_flags, in_reqs, n_res);
5387  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
5388  (void)attr; /* avoid potential warning */
5389  x86_insn_size_t size = X86_SIZE_32;
5390  init_ia32_attributes(res, size);
5391  set_ia32_am_support(res, ia32_am_binary);
5392  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
5393  out_infos[0].req = &ia32_requirements_gp_esp_I;
5394  out_infos[1].req = &ia32_class_reg_req_gp;
5395  out_infos[2].req = &arch_memory_requirement;
5396 
5397  verify_new_node(res);
5398  return optimize_node(res);
5399 }
5400 
5401 ir_node *new_bd_ia32_Subs(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *minuend, ir_node *subtrahend, x86_insn_size_t size)
5402 {
5403  static arch_register_req_t const *in_reqs[] = {
5404  &ia32_class_reg_req_gp,
5405  &ia32_class_reg_req_gp,
5406  &arch_memory_requirement,
5407  &ia32_class_reg_req_xmm,
5408  &ia32_class_reg_req_xmm,
5409  };
5410 
5411  /* construct in array */
5412  ir_node *const in[] = {
5413  base,
5414  index,
5415  mem,
5416  minuend,
5417  subtrahend,
5418  };
5419 
5420  ir_graph *const irg = get_irn_irg(block);
5421  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Subs, ia32_mode_float64, 5, in);
5422 
5423  /* init node attributes */
5424 
5425  /* flags */
5426  arch_irn_flags_t irn_flags = arch_irn_flags_none;
5427  irn_flags |= arch_irn_flag_rematerializable;
5428  int const n_res = 3;
5429  be_info_init_irn(res, irn_flags, in_reqs, n_res);
5430  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
5431  (void)attr; /* avoid potential warning */
5432  init_ia32_attributes(res, size);
5433  set_ia32_am_support(res, ia32_am_binary);
5434  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
5435  out_infos[0].req = &ia32_requirements_xmm_in_r3;
5436  out_infos[1].req = &ia32_class_reg_req_flags;
5437  out_infos[2].req = &arch_memory_requirement;
5438 
5439  verify_new_node(res);
5440  return optimize_node(res);
5441 }
5442 
5443 ir_node *new_bd_ia32_SwitchJmp(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, int n_res, const ir_switch_table *switch_table, const ir_entity *table_entity)
5444 {
5445  static arch_register_req_t const *in_reqs[] = {
5446  &ia32_class_reg_req_gp,
5447  &ia32_class_reg_req_gp,
5448  };
5449 
5450  /* construct in array */
5451  ir_node *const in[] = {
5452  base,
5453  index,
5454  };
5455 
5456  ir_graph *const irg = get_irn_irg(block);
5457  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_SwitchJmp, mode_T, 2, in);
5458 
5459  /* init node attributes */
5460 
5461  /* flags */
5462  arch_irn_flags_t irn_flags = arch_irn_flags_none;
5463  be_info_init_irn(res, irn_flags, in_reqs, n_res);
5464  ia32_switch_attr_t *const attr = (ia32_switch_attr_t*)get_irn_generic_attr(res);
5465  (void)attr; /* avoid potential warning */
5466  x86_insn_size_t const size = X86_SIZE_32;
5467  init_ia32_attributes(res, size);
5468  init_ia32_switch_attributes(res, switch_table, table_entity);
5469 
5470  verify_new_node(res);
5471  return optimize_node(res);
5472 }
5473 
5474 ir_node *new_bd_ia32_Test(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size, bool ins_permuted)
5475 {
5476  static arch_register_req_t const *in_reqs[] = {
5477  &ia32_class_reg_req_gp,
5478  &ia32_class_reg_req_gp,
5479  &arch_memory_requirement,
5480  &ia32_class_reg_req_gp,
5481  &ia32_class_reg_req_gp,
5482  };
5483 
5484  /* construct in array */
5485  ir_node *const in[] = {
5486  base,
5487  index,
5488  mem,
5489  left,
5490  right,
5491  };
5492 
5493  ir_graph *const irg = get_irn_irg(block);
5494  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Test, ia32_mode_flags, 5, in);
5495 
5496  /* init node attributes */
5497 
5498  /* flags */
5499  arch_irn_flags_t irn_flags = arch_irn_flags_none;
5500  irn_flags |= arch_irn_flag_modify_flags;
5501  irn_flags |= arch_irn_flag_rematerializable;
5502  int const n_res = 3;
5503  be_info_init_irn(res, irn_flags, in_reqs, n_res);
5504  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
5505  (void)attr; /* avoid potential warning */
5506  init_ia32_attributes(res, size);
5507  set_ia32_am_support(res, ia32_am_binary);
5508  attr->ins_permuted = ins_permuted;
5509  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
5510  out_infos[0].req = &ia32_class_reg_req_flags;
5511  out_infos[1].req = &arch_no_requirement;
5512  out_infos[2].req = &arch_memory_requirement;
5513 
5514  verify_new_node(res);
5515  return optimize_node(res);
5516 }
5517 
5518 ir_node *new_bd_ia32_Test_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size, bool ins_permuted)
5519 {
5520  static arch_register_req_t const *in_reqs[] = {
5521  &ia32_class_reg_req_gp,
5522  &ia32_class_reg_req_gp,
5523  &arch_memory_requirement,
5524  &ia32_requirements_gp_eax_ebx_ecx_edx,
5525  &ia32_requirements_gp_eax_ebx_ecx_edx,
5526  };
5527 
5528  /* construct in array */
5529  ir_node *const in[] = {
5530  base,
5531  index,
5532  mem,
5533  left,
5534  right,
5535  };
5536 
5537  ir_graph *const irg = get_irn_irg(block);
5538  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Test, ia32_mode_flags, 5, in);
5539 
5540  /* init node attributes */
5541 
5542  /* flags */
5543  arch_irn_flags_t irn_flags = arch_irn_flags_none;
5544  irn_flags |= arch_irn_flag_modify_flags;
5545  irn_flags |= arch_irn_flag_rematerializable;
5546  int const n_res = 3;
5547  be_info_init_irn(res, irn_flags, in_reqs, n_res);
5548  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
5549  (void)attr; /* avoid potential warning */
5550  init_ia32_attributes(res, size);
5551  set_ia32_am_support(res, ia32_am_binary);
5552  attr->ins_permuted = ins_permuted;
5553  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
5554  out_infos[0].req = &ia32_class_reg_req_flags;
5555  out_infos[1].req = &arch_no_requirement;
5556  out_infos[2].req = &arch_memory_requirement;
5557 
5558  verify_new_node(res);
5559  return optimize_node(res);
5560 }
5561 
5562 ir_node *new_bd_ia32_UD2(dbg_info *dbgi, ir_node *block, ir_node *mem)
5563 {
5564  static arch_register_req_t const *in_reqs[] = {
5565  &arch_memory_requirement,
5566  };
5567 
5568  /* construct in array */
5569  ir_node *const in[] = {
5570  mem,
5571  };
5572 
5573  ir_graph *const irg = get_irn_irg(block);
5574  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_UD2, mode_M, 1, in);
5575 
5576  /* init node attributes */
5577 
5578  /* flags */
5579  arch_irn_flags_t irn_flags = arch_irn_flags_none;
5580  int const n_res = 1;
5581  be_info_init_irn(res, irn_flags, in_reqs, n_res);
5582  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
5583  (void)attr; /* avoid potential warning */
5584  x86_insn_size_t const size = X86_SIZE_32;
5585  init_ia32_attributes(res, size);
5586  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
5587  out_infos[0].req = &arch_memory_requirement;
5588 
5589  verify_new_node(res);
5590  return optimize_node(res);
5591 }
5592 
5593 ir_node *new_bd_ia32_Ucomis(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, bool ins_permuted)
5594 {
5595  static arch_register_req_t const *in_reqs[] = {
5596  &ia32_class_reg_req_gp,
5597  &ia32_class_reg_req_gp,
5598  &arch_memory_requirement,
5599  &ia32_class_reg_req_xmm,
5600  &ia32_class_reg_req_xmm,
5601  };
5602 
5603  /* construct in array */
5604  ir_node *const in[] = {
5605  base,
5606  index,
5607  mem,
5608  left,
5609  right,
5610  };
5611 
5612  ir_graph *const irg = get_irn_irg(block);
5613  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Ucomis, ia32_mode_flags, 5, in);
5614 
5615  /* init node attributes */
5616 
5617  /* flags */
5618  arch_irn_flags_t irn_flags = arch_irn_flags_none;
5619  irn_flags |= arch_irn_flag_modify_flags;
5620  irn_flags |= arch_irn_flag_rematerializable;
5621  int const n_res = 1;
5622  be_info_init_irn(res, irn_flags, in_reqs, n_res);
5623  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
5624  (void)attr; /* avoid potential warning */
5625  x86_insn_size_t const size = X86_SIZE_32;
5626  init_ia32_attributes(res, size);
5627  set_ia32_am_support(res, ia32_am_binary);
5628  attr->ins_permuted = ins_permuted;
5629  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
5630  out_infos[0].req = &ia32_class_reg_req_flags;
5631 
5632  verify_new_node(res);
5633  return optimize_node(res);
5634 }
5635 
5636 ir_node *new_bd_ia32_Xor(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size)
5637 {
5638  static arch_register_req_t const *in_reqs[] = {
5639  &ia32_class_reg_req_gp,
5640  &ia32_class_reg_req_gp,
5641  &arch_memory_requirement,
5642  &ia32_class_reg_req_gp,
5643  &ia32_class_reg_req_gp,
5644  };
5645 
5646  /* construct in array */
5647  ir_node *const in[] = {
5648  base,
5649  index,
5650  mem,
5651  left,
5652  right,
5653  };
5654 
5655  ir_graph *const irg = get_irn_irg(block);
5656  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Xor, ia32_mode_gp, 5, in);
5657 
5658  /* init node attributes */
5659 
5660  /* flags */
5661  arch_irn_flags_t irn_flags = arch_irn_flags_none;
5662  irn_flags |= arch_irn_flag_modify_flags;
5663  irn_flags |= arch_irn_flag_rematerializable;
5664  int const n_res = 3;
5665  be_info_init_irn(res, irn_flags, in_reqs, n_res);
5666  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
5667  (void)attr; /* avoid potential warning */
5668  init_ia32_attributes(res, size);
5669  set_ia32_am_support(res, ia32_am_binary);
5670  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
5671  out_infos[0].req = &ia32_requirements_gp_in_r3_in_r4;
5672  out_infos[1].req = &ia32_class_reg_req_flags;
5673  out_infos[2].req = &arch_memory_requirement;
5674 
5675  verify_new_node(res);
5676  return optimize_node(res);
5677 }
5678 
5679 ir_node *new_bd_ia32_Xor_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size)
5680 {
5681  static arch_register_req_t const *in_reqs[] = {
5682  &ia32_class_reg_req_gp,
5683  &ia32_class_reg_req_gp,
5684  &arch_memory_requirement,
5685  &ia32_requirements_gp_eax_ebx_ecx_edx,
5686  &ia32_requirements_gp_eax_ebx_ecx_edx,
5687  };
5688 
5689  /* construct in array */
5690  ir_node *const in[] = {
5691  base,
5692  index,
5693  mem,
5694  left,
5695  right,
5696  };
5697 
5698  ir_graph *const irg = get_irn_irg(block);
5699  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Xor, ia32_mode_gp, 5, in);
5700 
5701  /* init node attributes */
5702 
5703  /* flags */
5704  arch_irn_flags_t irn_flags = arch_irn_flags_none;
5705  irn_flags |= arch_irn_flag_modify_flags;
5706  irn_flags |= arch_irn_flag_rematerializable;
5707  int const n_res = 3;
5708  be_info_init_irn(res, irn_flags, in_reqs, n_res);
5709  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
5710  (void)attr; /* avoid potential warning */
5711  init_ia32_attributes(res, size);
5712  set_ia32_am_support(res, ia32_am_binary);
5713  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
5714  out_infos[0].req = &ia32_requirements_gp_eax_ebx_ecx_edx_in_r3_in_r4;
5715  out_infos[1].req = &ia32_class_reg_req_flags;
5716  out_infos[2].req = &arch_memory_requirement;
5717 
5718  verify_new_node(res);
5719  return optimize_node(res);
5720 }
5721 
5722 ir_node *new_bd_ia32_Xor0(dbg_info *dbgi, ir_node *block, x86_insn_size_t size)
5723 {
5724  arch_register_req_t const **const in_reqs = NULL;
5725 
5726 
5727  ir_graph *const irg = get_irn_irg(block);
5728  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Xor0, ia32_mode_gp, 0, NULL);
5729 
5730  /* init node attributes */
5731 
5732  /* flags */
5733  arch_irn_flags_t irn_flags = arch_irn_flags_none;
5734  irn_flags |= arch_irn_flag_modify_flags;
5735  irn_flags |= arch_irn_flag_rematerializable;
5736  int const n_res = 2;
5737  be_info_init_irn(res, irn_flags, in_reqs, n_res);
5738  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
5739  (void)attr; /* avoid potential warning */
5740  init_ia32_attributes(res, size);
5741  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
5742  out_infos[0].req = &ia32_class_reg_req_gp;
5743  out_infos[1].req = &ia32_class_reg_req_flags;
5744 
5745  verify_new_node(res);
5746  return optimize_node(res);
5747 }
5748 
5749 ir_node *new_bd_ia32_XorHighLow(dbg_info *dbgi, ir_node *block, ir_node *value)
5750 {
5751  static arch_register_req_t const *in_reqs[] = {
5752  &ia32_requirements_gp_eax_ebx_ecx_edx,
5753  };
5754 
5755  /* construct in array */
5756  ir_node *const in[] = {
5757  value,
5758  };
5759 
5760  ir_graph *const irg = get_irn_irg(block);
5761  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_XorHighLow, mode_T, 1, in);
5762 
5763  /* init node attributes */
5764 
5765  /* flags */
5766  arch_irn_flags_t irn_flags = arch_irn_flags_none;
5767  irn_flags |= arch_irn_flag_modify_flags;
5768  irn_flags |= arch_irn_flag_rematerializable;
5769  int const n_res = 2;
5770  be_info_init_irn(res, irn_flags, in_reqs, n_res);
5771  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
5772  (void)attr; /* avoid potential warning */
5773  x86_insn_size_t const size = X86_SIZE_8;
5774  init_ia32_attributes(res, size);
5775  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
5776  out_infos[0].req = &ia32_requirements_gp_eax_ebx_ecx_edx_in_r0;
5777  out_infos[1].req = &ia32_class_reg_req_flags;
5778 
5779  verify_new_node(res);
5780  return optimize_node(res);
5781 }
5782 
5783 ir_node *new_bd_ia32_XorMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size)
5784 {
5785  static arch_register_req_t const *in_reqs[] = {
5786  &ia32_class_reg_req_gp,
5787  &ia32_class_reg_req_gp,
5788  &arch_memory_requirement,
5789  &ia32_class_reg_req_gp,
5790  };
5791 
5792  /* construct in array */
5793  ir_node *const in[] = {
5794  base,
5795  index,
5796  mem,
5797  val,
5798  };
5799 
5800  ir_graph *const irg = get_irn_irg(block);
5801  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_XorMem, mode_T, 4, in);
5802 
5803  /* init node attributes */
5804 
5805  /* flags */
5806  arch_irn_flags_t irn_flags = arch_irn_flags_none;
5807  irn_flags |= arch_irn_flag_modify_flags;
5808  irn_flags |= arch_irn_flag_rematerializable;
5809  int const n_res = 3;
5810  be_info_init_irn(res, irn_flags, in_reqs, n_res);
5811  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
5812  (void)attr; /* avoid potential warning */
5813  init_ia32_attributes(res, size);
5814  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
5815  out_infos[0].req = &arch_no_requirement;
5816  out_infos[1].req = &ia32_class_reg_req_flags;
5817  out_infos[2].req = &arch_memory_requirement;
5818 
5819  verify_new_node(res);
5820  return optimize_node(res);
5821 }
5822 
5823 ir_node *new_bd_ia32_XorMem_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size)
5824 {
5825  static arch_register_req_t const *in_reqs[] = {
5826  &ia32_class_reg_req_gp,
5827  &ia32_class_reg_req_gp,
5828  &arch_memory_requirement,
5829  &ia32_requirements_gp_eax_ebx_ecx_edx,
5830  };
5831 
5832  /* construct in array */
5833  ir_node *const in[] = {
5834  base,
5835  index,
5836  mem,
5837  val,
5838  };
5839 
5840  ir_graph *const irg = get_irn_irg(block);
5841  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_XorMem, mode_T, 4, in);
5842 
5843  /* init node attributes */
5844 
5845  /* flags */
5846  arch_irn_flags_t irn_flags = arch_irn_flags_none;
5847  irn_flags |= arch_irn_flag_modify_flags;
5848  irn_flags |= arch_irn_flag_rematerializable;
5849  int const n_res = 3;
5850  be_info_init_irn(res, irn_flags, in_reqs, n_res);
5851  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
5852  (void)attr; /* avoid potential warning */
5853  init_ia32_attributes(res, size);
5854  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
5855  out_infos[0].req = &arch_no_requirement;
5856  out_infos[1].req = &ia32_class_reg_req_flags;
5857  out_infos[2].req = &arch_memory_requirement;
5858 
5859  verify_new_node(res);
5860  return optimize_node(res);
5861 }
5862 
5863 ir_node *new_bd_ia32_Xorp(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size)
5864 {
5865  static arch_register_req_t const *in_reqs[] = {
5866  &ia32_class_reg_req_gp,
5867  &ia32_class_reg_req_gp,
5868  &arch_memory_requirement,
5869  &ia32_class_reg_req_xmm,
5870  &ia32_class_reg_req_xmm,
5871  };
5872 
5873  /* construct in array */
5874  ir_node *const in[] = {
5875  base,
5876  index,
5877  mem,
5878  left,
5879  right,
5880  };
5881 
5882  ir_graph *const irg = get_irn_irg(block);
5883  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Xorp, ia32_mode_float64, 5, in);
5884 
5885  /* init node attributes */
5886 
5887  /* flags */
5888  arch_irn_flags_t irn_flags = arch_irn_flags_none;
5889  irn_flags |= arch_irn_flag_rematerializable;
5890  int const n_res = 3;
5891  be_info_init_irn(res, irn_flags, in_reqs, n_res);
5892  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
5893  (void)attr; /* avoid potential warning */
5894  init_ia32_attributes(res, size);
5895  set_ia32_am_support(res, ia32_am_binary);
5896  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
5897  out_infos[0].req = &ia32_requirements_xmm_in_r3_in_r4;
5898  out_infos[1].req = &ia32_class_reg_req_flags;
5899  out_infos[2].req = &arch_memory_requirement;
5900 
5901  verify_new_node(res);
5902  return optimize_node(res);
5903 }
5904 
5905 ir_node *new_bd_ia32_emms(dbg_info *dbgi, ir_node *block)
5906 {
5907  arch_register_req_t const **const in_reqs = NULL;
5908 
5909 
5910  ir_graph *const irg = get_irn_irg(block);
5911  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_emms, mode_ANY, 0, NULL);
5912 
5913  /* init node attributes */
5914 
5915  /* flags */
5916  arch_irn_flags_t irn_flags = arch_irn_flags_none;
5917  int const n_res = 1;
5918  be_info_init_irn(res, irn_flags, in_reqs, n_res);
5919  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
5920  (void)attr; /* avoid potential warning */
5921  x86_insn_size_t const size = X86_SIZE_32; ia32_request_x87_sim(irg);
5922  init_ia32_attributes(res, size);
5923  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
5924  out_infos[0].req = &arch_no_requirement;
5925 
5926  verify_new_node(res);
5927  return optimize_node(res);
5928 }
5929 
5930 ir_node *new_bd_ia32_fabs(dbg_info *dbgi, ir_node *block, ir_node *value)
5931 {
5932  static arch_register_req_t const *in_reqs[] = {
5933  &ia32_class_reg_req_fp,
5934  };
5935 
5936  /* construct in array */
5937  ir_node *const in[] = {
5938  value,
5939  };
5940 
5941  ir_graph *const irg = get_irn_irg(block);
5942  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_fabs, x86_mode_E, 1, in);
5943 
5944  /* init node attributes */
5945 
5946  /* flags */
5947  arch_irn_flags_t irn_flags = arch_irn_flags_none;
5948  irn_flags |= arch_irn_flag_rematerializable;
5949  int const n_res = 1;
5950  be_info_init_irn(res, irn_flags, in_reqs, n_res);
5951  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
5952  (void)attr; /* avoid potential warning */
5953  x86_insn_size_t const size = X86_SIZE_80;
5954  init_ia32_attributes(res, size);
5955  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
5956  out_infos[0].req = &ia32_class_reg_req_fp;
5957 
5958  verify_new_node(res);
5959  return optimize_node(res);
5960 }
5961 
5962 ir_node *new_bd_ia32_fadd(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, ir_node *fpcw, x86_insn_size_t size)
5963 {
5964  static arch_register_req_t const *in_reqs[] = {
5965  &ia32_class_reg_req_gp,
5966  &ia32_class_reg_req_gp,
5967  &arch_memory_requirement,
5968  &ia32_class_reg_req_fp,
5969  &ia32_class_reg_req_fp,
5970  &ia32_class_reg_req_fpcw,
5971  };
5972 
5973  /* construct in array */
5974  ir_node *const in[] = {
5975  base,
5976  index,
5977  mem,
5978  left,
5979  right,
5980  fpcw,
5981  };
5982 
5983  ir_graph *const irg = get_irn_irg(block);
5984  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_fadd, x86_mode_E, 6, in);
5985 
5986  /* init node attributes */
5987 
5988  /* flags */
5989  arch_irn_flags_t irn_flags = arch_irn_flags_none;
5990  int const n_res = 3;
5991  be_info_init_irn(res, irn_flags, in_reqs, n_res);
5992  ia32_x87_attr_t *const attr = (ia32_x87_attr_t*)get_irn_generic_attr(res);
5993  (void)attr; /* avoid potential warning */
5994  init_ia32_attributes(res, size);
5995  init_ia32_x87_attributes(res);
5996  set_ia32_am_support(res, ia32_am_binary);
5997  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
5998  out_infos[0].req = &ia32_class_reg_req_fp;
5999  out_infos[1].req = &arch_no_requirement;
6000  out_infos[2].req = &arch_memory_requirement;
6001 
6002  verify_new_node(res);
6003  return optimize_node(res);
6004 }
6005 
6006 ir_node *new_bd_ia32_fchs(dbg_info *dbgi, ir_node *block, ir_node *value)
6007 {
6008  static arch_register_req_t const *in_reqs[] = {
6009  &ia32_class_reg_req_fp,
6010  };
6011 
6012  /* construct in array */
6013  ir_node *const in[] = {
6014  value,
6015  };
6016 
6017  ir_graph *const irg = get_irn_irg(block);
6018  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_fchs, x86_mode_E, 1, in);
6019 
6020  /* init node attributes */
6021 
6022  /* flags */
6023  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6024  irn_flags |= arch_irn_flag_rematerializable;
6025  int const n_res = 1;
6026  be_info_init_irn(res, irn_flags, in_reqs, n_res);
6027  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
6028  (void)attr; /* avoid potential warning */
6029  x86_insn_size_t const size = X86_SIZE_80;
6030  init_ia32_attributes(res, size);
6031  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
6032  out_infos[0].req = &ia32_class_reg_req_fp;
6033 
6034  verify_new_node(res);
6035  return optimize_node(res);
6036 }
6037 
6038 ir_node *new_bd_ia32_fdiv(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, ir_node *fpcw, x86_insn_size_t size)
6039 {
6040  static arch_register_req_t const *in_reqs[] = {
6041  &ia32_class_reg_req_gp,
6042  &ia32_class_reg_req_gp,
6043  &arch_memory_requirement,
6044  &ia32_class_reg_req_fp,
6045  &ia32_class_reg_req_fp,
6046  &ia32_class_reg_req_fpcw,
6047  };
6048 
6049  /* construct in array */
6050  ir_node *const in[] = {
6051  base,
6052  index,
6053  mem,
6054  left,
6055  right,
6056  fpcw,
6057  };
6058 
6059  ir_graph *const irg = get_irn_irg(block);
6060  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_fdiv, mode_T, 6, in);
6061 
6062  /* init node attributes */
6063 
6064  /* flags */
6065  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6066  int const n_res = 3;
6067  be_info_init_irn(res, irn_flags, in_reqs, n_res);
6068  ia32_x87_attr_t *const attr = (ia32_x87_attr_t*)get_irn_generic_attr(res);
6069  (void)attr; /* avoid potential warning */
6070  init_ia32_attributes(res, size);
6071  init_ia32_x87_attributes(res);
6072  set_ia32_am_support(res, ia32_am_binary);
6073  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
6074  out_infos[0].req = &ia32_class_reg_req_fp;
6075  out_infos[1].req = &arch_no_requirement;
6076  out_infos[2].req = &arch_memory_requirement;
6077 
6078  verify_new_node(res);
6079  return optimize_node(res);
6080 }
6081 
6082 ir_node *new_bd_ia32_fdup(dbg_info *dbgi, ir_node *block, ir_node *val, const arch_register_t *reg)
6083 {
6084  static arch_register_req_t const *in_reqs[] = {
6085  &ia32_class_reg_req_fp,
6086  };
6087 
6088  /* construct in array */
6089  ir_node *const in[] = {
6090  val,
6091  };
6092 
6093  ir_graph *const irg = get_irn_irg(block);
6094  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_fdup, x86_mode_E, 1, in);
6095 
6096  /* init node attributes */
6097 
6098  /* flags */
6099  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6100  int const n_res = 1;
6101  be_info_init_irn(res, irn_flags, in_reqs, n_res);
6102  ia32_x87_attr_t *const attr = (ia32_x87_attr_t*)get_irn_generic_attr(res);
6103  (void)attr; /* avoid potential warning */
6104  x86_insn_size_t const size = X86_SIZE_80;
6105  init_ia32_attributes(res, size);
6106  init_ia32_x87_attributes(res);
6107  attr->x87.reg = reg;
6108  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
6109  out_infos[0].req = &ia32_class_reg_req_fp;
6110 
6111  verify_new_node(res);
6112  return optimize_node(res);
6113 }
6114 
6115 ir_node *new_bd_ia32_femms(dbg_info *dbgi, ir_node *block)
6116 {
6117  arch_register_req_t const **const in_reqs = NULL;
6118 
6119 
6120  ir_graph *const irg = get_irn_irg(block);
6121  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_femms, mode_ANY, 0, NULL);
6122 
6123  /* init node attributes */
6124 
6125  /* flags */
6126  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6127  int const n_res = 1;
6128  be_info_init_irn(res, irn_flags, in_reqs, n_res);
6129  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
6130  (void)attr; /* avoid potential warning */
6131  x86_insn_size_t const size = X86_SIZE_32; ia32_request_x87_sim(irg);
6132  init_ia32_attributes(res, size);
6133  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
6134  out_infos[0].req = &arch_no_requirement;
6135 
6136  verify_new_node(res);
6137  return optimize_node(res);
6138 }
6139 
6140 ir_node *new_bd_ia32_ffreep(dbg_info *dbgi, ir_node *block, const arch_register_t *reg)
6141 {
6142  arch_register_req_t const **const in_reqs = NULL;
6143 
6144 
6145  ir_graph *const irg = get_irn_irg(block);
6146  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_ffreep, mode_ANY, 0, NULL);
6147 
6148  /* init node attributes */
6149 
6150  /* flags */
6151  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6152  int const n_res = 1;
6153  be_info_init_irn(res, irn_flags, in_reqs, n_res);
6154  ia32_x87_attr_t *const attr = (ia32_x87_attr_t*)get_irn_generic_attr(res);
6155  (void)attr; /* avoid potential warning */
6156  x86_insn_size_t const size = X86_SIZE_80;
6157  init_ia32_attributes(res, size);
6158  init_ia32_x87_attributes(res);
6159  attr->x87.reg = reg;
6160  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
6161  out_infos[0].req = &arch_no_requirement;
6162 
6163  verify_new_node(res);
6164  return optimize_node(res);
6165 }
6166 
6167 ir_node *new_bd_ia32_fild(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, x86_insn_size_t size)
6168 {
6169  static arch_register_req_t const *in_reqs[] = {
6170  &ia32_class_reg_req_gp,
6171  &ia32_class_reg_req_gp,
6172  &arch_memory_requirement,
6173  };
6174 
6175  /* construct in array */
6176  ir_node *const in[] = {
6177  base,
6178  index,
6179  mem,
6180  };
6181 
6182  ir_graph *const irg = get_irn_irg(block);
6183  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_fild, mode_T, 3, in);
6184 
6185  /* init node attributes */
6186 
6187  /* flags */
6188  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6189  int const n_res = 5;
6190  be_info_init_irn(res, irn_flags, in_reqs, n_res);
6191  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
6192  (void)attr; /* avoid potential warning */
6193  ia32_request_x87_sim(irg);
6194  init_ia32_attributes(res, size);
6195  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
6196  out_infos[0].req = &ia32_class_reg_req_fp;
6197  out_infos[1].req = &arch_no_requirement;
6198  out_infos[2].req = &arch_memory_requirement;
6199  out_infos[3].req = &arch_exec_requirement;
6200  out_infos[4].req = &arch_exec_requirement;
6201 
6202  verify_new_node(res);
6203  return optimize_node(res);
6204 }
6205 
6206 ir_node *new_bd_ia32_fist(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, ir_node *fpcw, x86_insn_size_t size)
6207 {
6208  static arch_register_req_t const *in_reqs[] = {
6209  &ia32_class_reg_req_gp,
6210  &ia32_class_reg_req_gp,
6211  &arch_memory_requirement,
6212  &ia32_class_reg_req_fp,
6213  &ia32_class_reg_req_fpcw,
6214  };
6215 
6216  /* construct in array */
6217  ir_node *const in[] = {
6218  base,
6219  index,
6220  mem,
6221  val,
6222  fpcw,
6223  };
6224 
6225  ir_graph *const irg = get_irn_irg(block);
6226  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_fist, mode_T, 5, in);
6227 
6228  /* init node attributes */
6229 
6230  /* flags */
6231  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6232  int const n_res = 3;
6233  be_info_init_irn(res, irn_flags, in_reqs, n_res);
6234  ia32_x87_attr_t *const attr = (ia32_x87_attr_t*)get_irn_generic_attr(res);
6235  (void)attr; /* avoid potential warning */
6236  init_ia32_attributes(res, size);
6237  init_ia32_x87_attributes(res);
6238  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
6239  out_infos[0].req = &arch_memory_requirement;
6240  out_infos[1].req = &arch_exec_requirement;
6241  out_infos[2].req = &arch_exec_requirement;
6242 
6243  verify_new_node(res);
6244  return optimize_node(res);
6245 }
6246 
6247 ir_node *new_bd_ia32_fistp(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, ir_node *fpcw, x86_insn_size_t size)
6248 {
6249  static arch_register_req_t const *in_reqs[] = {
6250  &ia32_class_reg_req_gp,
6251  &ia32_class_reg_req_gp,
6252  &arch_memory_requirement,
6253  &ia32_requirements_fp_fp_K,
6254  &ia32_class_reg_req_fpcw,
6255  };
6256 
6257  /* construct in array */
6258  ir_node *const in[] = {
6259  base,
6260  index,
6261  mem,
6262  val,
6263  fpcw,
6264  };
6265 
6266  ir_graph *const irg = get_irn_irg(block);
6267  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_fistp, mode_T, 5, in);
6268 
6269  /* init node attributes */
6270 
6271  /* flags */
6272  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6273  int const n_res = 3;
6274  be_info_init_irn(res, irn_flags, in_reqs, n_res);
6275  ia32_x87_attr_t *const attr = (ia32_x87_attr_t*)get_irn_generic_attr(res);
6276  (void)attr; /* avoid potential warning */
6277  init_ia32_attributes(res, size);
6278  init_ia32_x87_attributes(res);
6279  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
6280  out_infos[0].req = &arch_memory_requirement;
6281  out_infos[1].req = &arch_exec_requirement;
6282  out_infos[2].req = &arch_exec_requirement;
6283 
6284  verify_new_node(res);
6285  return optimize_node(res);
6286 }
6287 
6288 ir_node *new_bd_ia32_fisttp(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size)
6289 {
6290  static arch_register_req_t const *in_reqs[] = {
6291  &ia32_class_reg_req_gp,
6292  &ia32_class_reg_req_gp,
6293  &arch_memory_requirement,
6294  &ia32_requirements_fp_fp_K,
6295  };
6296 
6297  /* construct in array */
6298  ir_node *const in[] = {
6299  base,
6300  index,
6301  mem,
6302  val,
6303  };
6304 
6305  ir_graph *const irg = get_irn_irg(block);
6306  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_fisttp, mode_T, 4, in);
6307 
6308  /* init node attributes */
6309 
6310  /* flags */
6311  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6312  int const n_res = 3;
6313  be_info_init_irn(res, irn_flags, in_reqs, n_res);
6314  ia32_x87_attr_t *const attr = (ia32_x87_attr_t*)get_irn_generic_attr(res);
6315  (void)attr; /* avoid potential warning */
6316  init_ia32_attributes(res, size);
6317  init_ia32_x87_attributes(res);
6318  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
6319  out_infos[0].req = &arch_memory_requirement;
6320  out_infos[1].req = &arch_exec_requirement;
6321  out_infos[2].req = &arch_exec_requirement;
6322 
6323  verify_new_node(res);
6324  return optimize_node(res);
6325 }
6326 
6327 ir_node *new_bd_ia32_fld(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, x86_insn_size_t size)
6328 {
6329  static arch_register_req_t const *in_reqs[] = {
6330  &ia32_class_reg_req_gp,
6331  &ia32_class_reg_req_gp,
6332  &arch_memory_requirement,
6333  };
6334 
6335  /* construct in array */
6336  ir_node *const in[] = {
6337  base,
6338  index,
6339  mem,
6340  };
6341 
6342  ir_graph *const irg = get_irn_irg(block);
6343  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_fld, mode_T, 3, in);
6344 
6345  /* init node attributes */
6346 
6347  /* flags */
6348  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6349  irn_flags |= arch_irn_flag_rematerializable;
6350  int const n_res = 5;
6351  be_info_init_irn(res, irn_flags, in_reqs, n_res);
6352  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
6353  (void)attr; /* avoid potential warning */
6354  ia32_request_x87_sim(irg);
6355  init_ia32_attributes(res, size);
6356  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
6357  out_infos[0].req = &ia32_class_reg_req_fp;
6358  out_infos[1].req = &arch_no_requirement;
6359  out_infos[2].req = &arch_memory_requirement;
6360  out_infos[3].req = &arch_exec_requirement;
6361  out_infos[4].req = &arch_exec_requirement;
6362 
6363  verify_new_node(res);
6364  return optimize_node(res);
6365 }
6366 
6367 ir_node *new_bd_ia32_fld1(dbg_info *dbgi, ir_node *block)
6368 {
6369  arch_register_req_t const **const in_reqs = NULL;
6370 
6371 
6372  ir_graph *const irg = get_irn_irg(block);
6373  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_fld1, x86_mode_E, 0, NULL);
6374 
6375  /* init node attributes */
6376 
6377  /* flags */
6378  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6379  irn_flags |= arch_irn_flag_rematerializable;
6380  int const n_res = 1;
6381  be_info_init_irn(res, irn_flags, in_reqs, n_res);
6382  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
6383  (void)attr; /* avoid potential warning */
6384  x86_insn_size_t const size = X86_SIZE_80;
6385  ia32_request_x87_sim(irg);
6386  init_ia32_attributes(res, size);
6387  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
6388  out_infos[0].req = &ia32_class_reg_req_fp;
6389 
6390  verify_new_node(res);
6391  return optimize_node(res);
6392 }
6393 
6394 ir_node *new_bd_ia32_fldl2e(dbg_info *dbgi, ir_node *block)
6395 {
6396  arch_register_req_t const **const in_reqs = NULL;
6397 
6398 
6399  ir_graph *const irg = get_irn_irg(block);
6400  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_fldl2e, x86_mode_E, 0, NULL);
6401 
6402  /* init node attributes */
6403 
6404  /* flags */
6405  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6406  irn_flags |= arch_irn_flag_rematerializable;
6407  int const n_res = 1;
6408  be_info_init_irn(res, irn_flags, in_reqs, n_res);
6409  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
6410  (void)attr; /* avoid potential warning */
6411  x86_insn_size_t const size = X86_SIZE_80;
6412  ia32_request_x87_sim(irg);
6413  init_ia32_attributes(res, size);
6414  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
6415  out_infos[0].req = &ia32_class_reg_req_fp;
6416 
6417  verify_new_node(res);
6418  return optimize_node(res);
6419 }
6420 
6421 ir_node *new_bd_ia32_fldl2t(dbg_info *dbgi, ir_node *block)
6422 {
6423  arch_register_req_t const **const in_reqs = NULL;
6424 
6425 
6426  ir_graph *const irg = get_irn_irg(block);
6427  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_fldl2t, x86_mode_E, 0, NULL);
6428 
6429  /* init node attributes */
6430 
6431  /* flags */
6432  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6433  irn_flags |= arch_irn_flag_rematerializable;
6434  int const n_res = 1;
6435  be_info_init_irn(res, irn_flags, in_reqs, n_res);
6436  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
6437  (void)attr; /* avoid potential warning */
6438  x86_insn_size_t const size = X86_SIZE_80;
6439  ia32_request_x87_sim(irg);
6440  init_ia32_attributes(res, size);
6441  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
6442  out_infos[0].req = &ia32_class_reg_req_fp;
6443 
6444  verify_new_node(res);
6445  return optimize_node(res);
6446 }
6447 
6448 ir_node *new_bd_ia32_fldlg2(dbg_info *dbgi, ir_node *block)
6449 {
6450  arch_register_req_t const **const in_reqs = NULL;
6451 
6452 
6453  ir_graph *const irg = get_irn_irg(block);
6454  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_fldlg2, x86_mode_E, 0, NULL);
6455 
6456  /* init node attributes */
6457 
6458  /* flags */
6459  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6460  irn_flags |= arch_irn_flag_rematerializable;
6461  int const n_res = 1;
6462  be_info_init_irn(res, irn_flags, in_reqs, n_res);
6463  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
6464  (void)attr; /* avoid potential warning */
6465  x86_insn_size_t const size = X86_SIZE_80;
6466  ia32_request_x87_sim(irg);
6467  init_ia32_attributes(res, size);
6468  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
6469  out_infos[0].req = &ia32_class_reg_req_fp;
6470 
6471  verify_new_node(res);
6472  return optimize_node(res);
6473 }
6474 
6475 ir_node *new_bd_ia32_fldln2(dbg_info *dbgi, ir_node *block)
6476 {
6477  arch_register_req_t const **const in_reqs = NULL;
6478 
6479 
6480  ir_graph *const irg = get_irn_irg(block);
6481  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_fldln2, x86_mode_E, 0, NULL);
6482 
6483  /* init node attributes */
6484 
6485  /* flags */
6486  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6487  irn_flags |= arch_irn_flag_rematerializable;
6488  int const n_res = 1;
6489  be_info_init_irn(res, irn_flags, in_reqs, n_res);
6490  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
6491  (void)attr; /* avoid potential warning */
6492  x86_insn_size_t const size = X86_SIZE_80;
6493  ia32_request_x87_sim(irg);
6494  init_ia32_attributes(res, size);
6495  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
6496  out_infos[0].req = &ia32_class_reg_req_fp;
6497 
6498  verify_new_node(res);
6499  return optimize_node(res);
6500 }
6501 
6502 ir_node *new_bd_ia32_fldpi(dbg_info *dbgi, ir_node *block)
6503 {
6504  arch_register_req_t const **const in_reqs = NULL;
6505 
6506 
6507  ir_graph *const irg = get_irn_irg(block);
6508  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_fldpi, x86_mode_E, 0, NULL);
6509 
6510  /* init node attributes */
6511 
6512  /* flags */
6513  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6514  irn_flags |= arch_irn_flag_rematerializable;
6515  int const n_res = 1;
6516  be_info_init_irn(res, irn_flags, in_reqs, n_res);
6517  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
6518  (void)attr; /* avoid potential warning */
6519  x86_insn_size_t const size = X86_SIZE_80;
6520  ia32_request_x87_sim(irg);
6521  init_ia32_attributes(res, size);
6522  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
6523  out_infos[0].req = &ia32_class_reg_req_fp;
6524 
6525  verify_new_node(res);
6526  return optimize_node(res);
6527 }
6528 
6529 ir_node *new_bd_ia32_fldz(dbg_info *dbgi, ir_node *block)
6530 {
6531  arch_register_req_t const **const in_reqs = NULL;
6532 
6533 
6534  ir_graph *const irg = get_irn_irg(block);
6535  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_fldz, x86_mode_E, 0, NULL);
6536 
6537  /* init node attributes */
6538 
6539  /* flags */
6540  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6541  irn_flags |= arch_irn_flag_rematerializable;
6542  int const n_res = 1;
6543  be_info_init_irn(res, irn_flags, in_reqs, n_res);
6544  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
6545  (void)attr; /* avoid potential warning */
6546  x86_insn_size_t const size = X86_SIZE_80;
6547  ia32_request_x87_sim(irg);
6548  init_ia32_attributes(res, size);
6549  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
6550  out_infos[0].req = &ia32_class_reg_req_fp;
6551 
6552  verify_new_node(res);
6553  return optimize_node(res);
6554 }
6555 
6556 ir_node *new_bd_ia32_fmul(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, ir_node *fpcw, x86_insn_size_t size)
6557 {
6558  static arch_register_req_t const *in_reqs[] = {
6559  &ia32_class_reg_req_gp,
6560  &ia32_class_reg_req_gp,
6561  &arch_memory_requirement,
6562  &ia32_class_reg_req_fp,
6563  &ia32_class_reg_req_fp,
6564  &ia32_class_reg_req_fpcw,
6565  };
6566 
6567  /* construct in array */
6568  ir_node *const in[] = {
6569  base,
6570  index,
6571  mem,
6572  left,
6573  right,
6574  fpcw,
6575  };
6576 
6577  ir_graph *const irg = get_irn_irg(block);
6578  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_fmul, x86_mode_E, 6, in);
6579 
6580  /* init node attributes */
6581 
6582  /* flags */
6583  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6584  int const n_res = 3;
6585  be_info_init_irn(res, irn_flags, in_reqs, n_res);
6586  ia32_x87_attr_t *const attr = (ia32_x87_attr_t*)get_irn_generic_attr(res);
6587  (void)attr; /* avoid potential warning */
6588  init_ia32_attributes(res, size);
6589  init_ia32_x87_attributes(res);
6590  set_ia32_am_support(res, ia32_am_binary);
6591  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
6592  out_infos[0].req = &ia32_class_reg_req_fp;
6593  out_infos[1].req = &arch_no_requirement;
6594  out_infos[2].req = &arch_memory_requirement;
6595 
6596  verify_new_node(res);
6597  return optimize_node(res);
6598 }
6599 
6600 ir_node *new_bd_ia32_fpop(dbg_info *dbgi, ir_node *block, const arch_register_t *reg)
6601 {
6602  arch_register_req_t const **const in_reqs = NULL;
6603 
6604 
6605  ir_graph *const irg = get_irn_irg(block);
6606  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_fpop, mode_ANY, 0, NULL);
6607 
6608  /* init node attributes */
6609 
6610  /* flags */
6611  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6612  int const n_res = 1;
6613  be_info_init_irn(res, irn_flags, in_reqs, n_res);
6614  ia32_x87_attr_t *const attr = (ia32_x87_attr_t*)get_irn_generic_attr(res);
6615  (void)attr; /* avoid potential warning */
6616  x86_insn_size_t const size = X86_SIZE_80;
6617  init_ia32_attributes(res, size);
6618  init_ia32_x87_attributes(res);
6619  attr->x87.reg = reg;
6620  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
6621  out_infos[0].req = &arch_no_requirement;
6622 
6623  verify_new_node(res);
6624  return optimize_node(res);
6625 }
6626 
6627 ir_node *new_bd_ia32_fst(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size)
6628 {
6629  static arch_register_req_t const *in_reqs[] = {
6630  &ia32_class_reg_req_gp,
6631  &ia32_class_reg_req_gp,
6632  &arch_memory_requirement,
6633  &ia32_class_reg_req_fp,
6634  };
6635 
6636  /* construct in array */
6637  ir_node *const in[] = {
6638  base,
6639  index,
6640  mem,
6641  val,
6642  };
6643 
6644  ir_graph *const irg = get_irn_irg(block);
6645  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_fst, mode_T, 4, in);
6646 
6647  /* init node attributes */
6648 
6649  /* flags */
6650  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6651  irn_flags |= arch_irn_flag_rematerializable;
6652  int const n_res = 3;
6653  be_info_init_irn(res, irn_flags, in_reqs, n_res);
6654  ia32_x87_attr_t *const attr = (ia32_x87_attr_t*)get_irn_generic_attr(res);
6655  (void)attr; /* avoid potential warning */
6656  init_ia32_attributes(res, size);
6657  init_ia32_x87_attributes(res);
6658  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
6659  out_infos[0].req = &arch_memory_requirement;
6660  out_infos[1].req = &arch_exec_requirement;
6661  out_infos[2].req = &arch_exec_requirement;
6662 
6663  verify_new_node(res);
6664  return optimize_node(res);
6665 }
6666 
6667 ir_node *new_bd_ia32_fstp(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size)
6668 {
6669  static arch_register_req_t const *in_reqs[] = {
6670  &ia32_class_reg_req_gp,
6671  &ia32_class_reg_req_gp,
6672  &arch_memory_requirement,
6673  &ia32_requirements_fp_fp_K,
6674  };
6675 
6676  /* construct in array */
6677  ir_node *const in[] = {
6678  base,
6679  index,
6680  mem,
6681  val,
6682  };
6683 
6684  ir_graph *const irg = get_irn_irg(block);
6685  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_fstp, mode_T, 4, in);
6686 
6687  /* init node attributes */
6688 
6689  /* flags */
6690  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6691  irn_flags |= arch_irn_flag_rematerializable;
6692  int const n_res = 3;
6693  be_info_init_irn(res, irn_flags, in_reqs, n_res);
6694  ia32_x87_attr_t *const attr = (ia32_x87_attr_t*)get_irn_generic_attr(res);
6695  (void)attr; /* avoid potential warning */
6696  init_ia32_attributes(res, size);
6697  init_ia32_x87_attributes(res);
6698  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
6699  out_infos[0].req = &arch_memory_requirement;
6700  out_infos[1].req = &arch_exec_requirement;
6701  out_infos[2].req = &arch_exec_requirement;
6702 
6703  verify_new_node(res);
6704  return optimize_node(res);
6705 }
6706 
6707 ir_node *new_bd_ia32_fsub(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, ir_node *fpcw, x86_insn_size_t size)
6708 {
6709  static arch_register_req_t const *in_reqs[] = {
6710  &ia32_class_reg_req_gp,
6711  &ia32_class_reg_req_gp,
6712  &arch_memory_requirement,
6713  &ia32_class_reg_req_fp,
6714  &ia32_class_reg_req_fp,
6715  &ia32_class_reg_req_fpcw,
6716  };
6717 
6718  /* construct in array */
6719  ir_node *const in[] = {
6720  base,
6721  index,
6722  mem,
6723  left,
6724  right,
6725  fpcw,
6726  };
6727 
6728  ir_graph *const irg = get_irn_irg(block);
6729  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_fsub, x86_mode_E, 6, in);
6730 
6731  /* init node attributes */
6732 
6733  /* flags */
6734  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6735  int const n_res = 3;
6736  be_info_init_irn(res, irn_flags, in_reqs, n_res);
6737  ia32_x87_attr_t *const attr = (ia32_x87_attr_t*)get_irn_generic_attr(res);
6738  (void)attr; /* avoid potential warning */
6739  init_ia32_attributes(res, size);
6740  init_ia32_x87_attributes(res);
6741  set_ia32_am_support(res, ia32_am_binary);
6742  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
6743  out_infos[0].req = &ia32_class_reg_req_fp;
6744  out_infos[1].req = &arch_no_requirement;
6745  out_infos[2].req = &arch_memory_requirement;
6746 
6747  verify_new_node(res);
6748  return optimize_node(res);
6749 }
6750 
6751 ir_node *new_bd_ia32_fxch(dbg_info *dbgi, ir_node *block, const arch_register_t *reg)
6752 {
6753  arch_register_req_t const **const in_reqs = NULL;
6754 
6755 
6756  ir_graph *const irg = get_irn_irg(block);
6757  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_fxch, mode_ANY, 0, NULL);
6758 
6759  /* init node attributes */
6760 
6761  /* flags */
6762  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6763  int const n_res = 1;
6764  be_info_init_irn(res, irn_flags, in_reqs, n_res);
6765  ia32_x87_attr_t *const attr = (ia32_x87_attr_t*)get_irn_generic_attr(res);
6766  (void)attr; /* avoid potential warning */
6767  x86_insn_size_t const size = X86_SIZE_80;
6768  init_ia32_attributes(res, size);
6769  init_ia32_x87_attributes(res);
6770  attr->x87.reg = reg;
6771  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
6772  out_infos[0].req = &arch_no_requirement;
6773 
6774  verify_new_node(res);
6775  return optimize_node(res);
6776 }
6777 
6778 ir_node *new_bd_ia32_l_Adc(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, ir_node *eflags, ir_mode *mode)
6779 {
6780 
6781  /* construct in array */
6782  ir_node *const in[] = {
6783  left,
6784  right,
6785  eflags,
6786  };
6787 
6788  ir_graph *const irg = get_irn_irg(block);
6789  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_l_Adc, mode, 3, in);
6790 
6791  /* init node attributes */
6792 
6793  verify_new_node(res);
6794  return optimize_node(res);
6795 }
6796 
6797 ir_node *new_bd_ia32_l_Add(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right)
6798 {
6799 
6800  /* construct in array */
6801  ir_node *const in[] = {
6802  left,
6803  right,
6804  };
6805 
6806  ir_graph *const irg = get_irn_irg(block);
6807  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_l_Add, mode_T, 2, in);
6808 
6809  /* init node attributes */
6810 
6811  verify_new_node(res);
6812  return optimize_node(res);
6813 }
6814 
6815 ir_node *new_bd_ia32_l_FloattoLL(dbg_info *dbgi, ir_node *block, ir_node *val)
6816 {
6817 
6818  /* construct in array */
6819  ir_node *const in[] = {
6820  val,
6821  };
6822 
6823  ir_graph *const irg = get_irn_irg(block);
6824  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_l_FloattoLL, mode_T, 1, in);
6825 
6826  /* init node attributes */
6827 
6828  verify_new_node(res);
6829  return optimize_node(res);
6830 }
6831 
6832 ir_node *new_bd_ia32_l_IMul(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right)
6833 {
6834 
6835  /* construct in array */
6836  ir_node *const in[] = {
6837  left,
6838  right,
6839  };
6840 
6841  ir_graph *const irg = get_irn_irg(block);
6842  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_l_IMul, mode_T, 2, in);
6843 
6844  /* init node attributes */
6845 
6846  verify_new_node(res);
6847  return optimize_node(res);
6848 }
6849 
6850 ir_node *new_bd_ia32_l_LLtoFloat(dbg_info *dbgi, ir_node *block, ir_node *val_high, ir_node *val_low, ir_mode *mode)
6851 {
6852 
6853  /* construct in array */
6854  ir_node *const in[] = {
6855  val_high,
6856  val_low,
6857  };
6858 
6859  ir_graph *const irg = get_irn_irg(block);
6860  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_l_LLtoFloat, mode, 2, in);
6861 
6862  /* init node attributes */
6863 
6864  verify_new_node(res);
6865  return optimize_node(res);
6866 }
6867 
6868 ir_node *new_bd_ia32_l_Minus64(dbg_info *dbgi, ir_node *block, ir_node *low, ir_node *high)
6869 {
6870 
6871  /* construct in array */
6872  ir_node *const in[] = {
6873  low,
6874  high,
6875  };
6876 
6877  ir_graph *const irg = get_irn_irg(block);
6878  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_l_Minus64, mode_T, 2, in);
6879 
6880  /* init node attributes */
6881 
6882  verify_new_node(res);
6883  return optimize_node(res);
6884 }
6885 
6886 ir_node *new_bd_ia32_l_Mul(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right)
6887 {
6888 
6889  /* construct in array */
6890  ir_node *const in[] = {
6891  left,
6892  right,
6893  };
6894 
6895  ir_graph *const irg = get_irn_irg(block);
6896  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_l_Mul, mode_T, 2, in);
6897 
6898  /* init node attributes */
6899 
6900  verify_new_node(res);
6901  return optimize_node(res);
6902 }
6903 
6904 ir_node *new_bd_ia32_l_Sbb(dbg_info *dbgi, ir_node *block, ir_node *minuend, ir_node *subtrahend, ir_node *eflags, ir_mode *mode)
6905 {
6906 
6907  /* construct in array */
6908  ir_node *const in[] = {
6909  minuend,
6910  subtrahend,
6911  eflags,
6912  };
6913 
6914  ir_graph *const irg = get_irn_irg(block);
6915  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_l_Sbb, mode, 3, in);
6916 
6917  /* init node attributes */
6918 
6919  verify_new_node(res);
6920  return optimize_node(res);
6921 }
6922 
6923 ir_node *new_bd_ia32_l_Sub(dbg_info *dbgi, ir_node *block, ir_node *minuend, ir_node *subtrahend)
6924 {
6925 
6926  /* construct in array */
6927  ir_node *const in[] = {
6928  minuend,
6929  subtrahend,
6930  };
6931 
6932  ir_graph *const irg = get_irn_irg(block);
6933  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_l_Sub, mode_T, 2, in);
6934 
6935  /* init node attributes */
6936 
6937  verify_new_node(res);
6938  return optimize_node(res);
6939 }
6940 
6941 ir_node *new_bd_ia32_xAllOnes(dbg_info *dbgi, ir_node *block, x86_insn_size_t size)
6942 {
6943  arch_register_req_t const **const in_reqs = NULL;
6944 
6945 
6946  ir_graph *const irg = get_irn_irg(block);
6947  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_xAllOnes, ia32_mode_float64, 0, NULL);
6948 
6949  /* init node attributes */
6950 
6951  /* flags */
6952  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6953  irn_flags |= arch_irn_flag_rematerializable;
6954  int const n_res = 1;
6955  be_info_init_irn(res, irn_flags, in_reqs, n_res);
6956  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
6957  (void)attr; /* avoid potential warning */
6958  init_ia32_attributes(res, size);
6959  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
6960  out_infos[0].req = &ia32_class_reg_req_xmm;
6961 
6962  verify_new_node(res);
6963  return optimize_node(res);
6964 }
6965 
6966 ir_node *new_bd_ia32_xLoad(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, x86_insn_size_t size)
6967 {
6968  static arch_register_req_t const *in_reqs[] = {
6969  &ia32_class_reg_req_gp,
6970  &ia32_class_reg_req_gp,
6971  &arch_memory_requirement,
6972  };
6973 
6974  /* construct in array */
6975  ir_node *const in[] = {
6976  base,
6977  index,
6978  mem,
6979  };
6980 
6981  ir_graph *const irg = get_irn_irg(block);
6982  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_xLoad, mode_T, 3, in);
6983 
6984  /* init node attributes */
6985 
6986  /* flags */
6987  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6988  int const n_res = 5;
6989  be_info_init_irn(res, irn_flags, in_reqs, n_res);
6990  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
6991  (void)attr; /* avoid potential warning */
6992  init_ia32_attributes(res, size);
6993  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
6994  out_infos[0].req = &ia32_class_reg_req_xmm;
6995  out_infos[1].req = &arch_no_requirement;
6996  out_infos[2].req = &arch_memory_requirement;
6997  out_infos[3].req = &arch_exec_requirement;
6998  out_infos[4].req = &arch_exec_requirement;
6999 
7000  verify_new_node(res);
7001  return optimize_node(res);
7002 }
7003 
7004 ir_node *new_bd_ia32_xPzero(dbg_info *dbgi, ir_node *block, x86_insn_size_t size)
7005 {
7006  arch_register_req_t const **const in_reqs = NULL;
7007 
7008 
7009  ir_graph *const irg = get_irn_irg(block);
7010  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_xPzero, ia32_mode_float64, 0, NULL);
7011 
7012  /* init node attributes */
7013 
7014  /* flags */
7015  arch_irn_flags_t irn_flags = arch_irn_flags_none;
7016  irn_flags |= arch_irn_flag_rematerializable;
7017  int const n_res = 1;
7018  be_info_init_irn(res, irn_flags, in_reqs, n_res);
7019  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
7020  (void)attr; /* avoid potential warning */
7021  init_ia32_attributes(res, size);
7022  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
7023  out_infos[0].req = &ia32_class_reg_req_xmm;
7024 
7025  verify_new_node(res);
7026  return optimize_node(res);
7027 }
7028 
7029 ir_node *new_bd_ia32_xStore(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size)
7030 {
7031  static arch_register_req_t const *in_reqs[] = {
7032  &ia32_class_reg_req_gp,
7033  &ia32_class_reg_req_gp,
7034  &arch_memory_requirement,
7035  &ia32_class_reg_req_xmm,
7036  };
7037 
7038  /* construct in array */
7039  ir_node *const in[] = {
7040  base,
7041  index,
7042  mem,
7043  val,
7044  };
7045 
7046  ir_graph *const irg = get_irn_irg(block);
7047  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_xStore, mode_T, 4, in);
7048 
7049  /* init node attributes */
7050 
7051  /* flags */
7052  arch_irn_flags_t irn_flags = arch_irn_flags_none;
7053  int const n_res = 3;
7054  be_info_init_irn(res, irn_flags, in_reqs, n_res);
7055  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
7056  (void)attr; /* avoid potential warning */
7057  init_ia32_attributes(res, size);
7058  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
7059  out_infos[0].req = &arch_memory_requirement;
7060  out_infos[1].req = &arch_exec_requirement;
7061  out_infos[2].req = &arch_exec_requirement;
7062 
7063  verify_new_node(res);
7064  return optimize_node(res);
7065 }
7066 
7067 ir_node *new_bd_ia32_xZero(dbg_info *dbgi, ir_node *block, x86_insn_size_t size)
7068 {
7069  arch_register_req_t const **const in_reqs = NULL;
7070 
7071 
7072  ir_graph *const irg = get_irn_irg(block);
7073  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_xZero, ia32_mode_float64, 0, NULL);
7074 
7075  /* init node attributes */
7076 
7077  /* flags */
7078  arch_irn_flags_t irn_flags = arch_irn_flags_none;
7079  irn_flags |= arch_irn_flag_rematerializable;
7080  int const n_res = 1;
7081  be_info_init_irn(res, irn_flags, in_reqs, n_res);
7082  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
7083  (void)attr; /* avoid potential warning */
7084  init_ia32_attributes(res, size);
7085  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
7086  out_infos[0].req = &ia32_class_reg_req_xmm;
7087 
7088  verify_new_node(res);
7089  return optimize_node(res);
7090 }
7091 
7092 ir_node *new_bd_ia32_xxLoad(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, x86_insn_size_t size)
7093 {
7094  static arch_register_req_t const *in_reqs[] = {
7095  &ia32_class_reg_req_gp,
7096  &ia32_class_reg_req_gp,
7097  &arch_memory_requirement,
7098  };
7099 
7100  /* construct in array */
7101  ir_node *const in[] = {
7102  base,
7103  index,
7104  mem,
7105  };
7106 
7107  ir_graph *const irg = get_irn_irg(block);
7108  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_xxLoad, mode_T, 3, in);
7109 
7110  /* init node attributes */
7111 
7112  /* flags */
7113  arch_irn_flags_t irn_flags = arch_irn_flags_none;
7114  int const n_res = 4;
7115  be_info_init_irn(res, irn_flags, in_reqs, n_res);
7116  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
7117  (void)attr; /* avoid potential warning */
7118  init_ia32_attributes(res, size);
7119  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
7120  out_infos[0].req = &ia32_class_reg_req_xmm;
7121  out_infos[1].req = &arch_memory_requirement;
7122  out_infos[2].req = &arch_exec_requirement;
7123  out_infos[3].req = &arch_exec_requirement;
7124 
7125  verify_new_node(res);
7126  return optimize_node(res);
7127 }
7128 
7129 ir_node *new_bd_ia32_xxStore(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size)
7130 {
7131  static arch_register_req_t const *in_reqs[] = {
7132  &ia32_class_reg_req_gp,
7133  &ia32_class_reg_req_gp,
7134  &arch_memory_requirement,
7135  &ia32_class_reg_req_xmm,
7136  };
7137 
7138  /* construct in array */
7139  ir_node *const in[] = {
7140  base,
7141  index,
7142  mem,
7143  val,
7144  };
7145 
7146  ir_graph *const irg = get_irn_irg(block);
7147  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_xxStore, mode_T, 4, in);
7148 
7149  /* init node attributes */
7150 
7151  /* flags */
7152  arch_irn_flags_t irn_flags = arch_irn_flags_none;
7153  int const n_res = 3;
7154  be_info_init_irn(res, irn_flags, in_reqs, n_res);
7155  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
7156  (void)attr; /* avoid potential warning */
7157  init_ia32_attributes(res, size);
7158  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
7159  out_infos[0].req = &arch_memory_requirement;
7160  out_infos[1].req = &arch_exec_requirement;
7161  out_infos[2].req = &arch_exec_requirement;
7162 
7163  verify_new_node(res);
7164  return optimize_node(res);
7165 }
7166 
7167 
7172 void ia32_create_opcodes(void)
7173 {
7174  ir_op *op;
7175  int cur_opcode = get_next_ir_opcodes(iro_ia32_last);
7176 
7177  ia32_opcode_start = cur_opcode;
7178  op = new_ir_op(cur_opcode + iro_ia32_Adc, "ia32_Adc", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_condcode_attr_t));
7179  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7180  set_op_attrs_equal(op, ia32_condcode_attrs_equal);
7181  set_op_copy_attr(op, be_copy_attr);
7182  set_op_tag(op, ia32_op_tag);
7183  ia32_init_op(op, 1);
7184  op_ia32_Adc = op;
7185  op = new_ir_op(cur_opcode + iro_ia32_Add, "ia32_Add", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7186  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7187  set_op_attrs_equal(op, ia32_attrs_equal);
7188  set_op_copy_attr(op, be_copy_attr);
7189  set_op_tag(op, ia32_op_tag);
7190  ia32_init_op(op, 1);
7191  op_ia32_Add = op;
7192  op = new_ir_op(cur_opcode + iro_ia32_AddMem, "ia32_AddMem", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7193  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7194  set_op_attrs_equal(op, ia32_attrs_equal);
7195  set_op_copy_attr(op, be_copy_attr);
7196  set_op_tag(op, ia32_op_tag);
7197  ia32_init_op(op, 1);
7198  op_ia32_AddMem = op;
7199  op = new_ir_op(cur_opcode + iro_ia32_AddSP, "ia32_AddSP", op_pin_state_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7200  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7201  set_op_attrs_equal(op, ia32_attrs_equal);
7202  set_op_copy_attr(op, be_copy_attr);
7203  set_op_tag(op, ia32_op_tag);
7204  ia32_init_op(op, 1);
7205  op_ia32_AddSP = op;
7206  op = new_ir_op(cur_opcode + iro_ia32_Adds, "ia32_Adds", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7207  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7208  set_op_attrs_equal(op, ia32_attrs_equal);
7209  set_op_copy_attr(op, be_copy_attr);
7210  set_op_tag(op, ia32_op_tag);
7211  ia32_init_op(op, 4);
7212  op_ia32_Adds = op;
7213  op = new_ir_op(cur_opcode + iro_ia32_And, "ia32_And", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7214  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7215  set_op_attrs_equal(op, ia32_attrs_equal);
7216  set_op_copy_attr(op, be_copy_attr);
7217  set_op_tag(op, ia32_op_tag);
7218  ia32_init_op(op, 1);
7219  op_ia32_And = op;
7220  op = new_ir_op(cur_opcode + iro_ia32_AndMem, "ia32_AndMem", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7221  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7222  set_op_attrs_equal(op, ia32_attrs_equal);
7223  set_op_copy_attr(op, be_copy_attr);
7224  set_op_tag(op, ia32_op_tag);
7225  ia32_init_op(op, 1);
7226  op_ia32_AndMem = op;
7227  op = new_ir_op(cur_opcode + iro_ia32_Andnp, "ia32_Andnp", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7228  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7229  set_op_attrs_equal(op, ia32_attrs_equal);
7230  set_op_copy_attr(op, be_copy_attr);
7231  set_op_tag(op, ia32_op_tag);
7232  ia32_init_op(op, 3);
7233  op_ia32_Andnp = op;
7234  op = new_ir_op(cur_opcode + iro_ia32_Andp, "ia32_Andp", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7235  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7236  set_op_attrs_equal(op, ia32_attrs_equal);
7237  set_op_copy_attr(op, be_copy_attr);
7238  set_op_tag(op, ia32_op_tag);
7239  ia32_init_op(op, 3);
7240  op_ia32_Andp = op;
7241  op = new_ir_op(cur_opcode + iro_ia32_Breakpoint, "ia32_Breakpoint", op_pin_state_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7242  ir_op_set_memory_index(op, 0); set_op_dump(op, ia32_dump_node);
7243  set_op_attrs_equal(op, ia32_attrs_equal);
7244  set_op_copy_attr(op, be_copy_attr);
7245  set_op_tag(op, ia32_op_tag);
7246  ia32_init_op(op, 0);
7247  op_ia32_Breakpoint = op;
7248  op = new_ir_op(cur_opcode + iro_ia32_Bsf, "ia32_Bsf", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7249  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7250  set_op_attrs_equal(op, ia32_attrs_equal);
7251  set_op_copy_attr(op, be_copy_attr);
7252  set_op_tag(op, ia32_op_tag);
7253  ia32_init_op(op, 1);
7254  op_ia32_Bsf = op;
7255  op = new_ir_op(cur_opcode + iro_ia32_Bsr, "ia32_Bsr", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7256  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7257  set_op_attrs_equal(op, ia32_attrs_equal);
7258  set_op_copy_attr(op, be_copy_attr);
7259  set_op_tag(op, ia32_op_tag);
7260  ia32_init_op(op, 1);
7261  op_ia32_Bsr = op;
7262  op = new_ir_op(cur_opcode + iro_ia32_Bswap, "ia32_Bswap", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7263  set_op_dump(op, ia32_dump_node);
7264  set_op_attrs_equal(op, ia32_attrs_equal);
7265  set_op_copy_attr(op, be_copy_attr);
7266  set_op_tag(op, ia32_op_tag);
7267  ia32_init_op(op, 1);
7268  op_ia32_Bswap = op;
7269  op = new_ir_op(cur_opcode + iro_ia32_Bswap16, "ia32_Bswap16", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7270  set_op_dump(op, ia32_dump_node);
7271  set_op_attrs_equal(op, ia32_attrs_equal);
7272  set_op_copy_attr(op, be_copy_attr);
7273  set_op_tag(op, ia32_op_tag);
7274  ia32_init_op(op, 1);
7275  op_ia32_Bswap16 = op;
7276  op = new_ir_op(cur_opcode + iro_ia32_Bt, "ia32_Bt", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7277  set_op_dump(op, ia32_dump_node);
7278  set_op_attrs_equal(op, ia32_attrs_equal);
7279  set_op_copy_attr(op, be_copy_attr);
7280  set_op_tag(op, ia32_op_tag);
7281  ia32_init_op(op, 1);
7282  op_ia32_Bt = op;
7283  op = new_ir_op(cur_opcode + iro_ia32_CMovcc, "ia32_CMovcc", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_condcode_attr_t));
7284  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7285  set_op_attrs_equal(op, ia32_condcode_attrs_equal);
7286  set_op_copy_attr(op, be_copy_attr);
7287  set_op_tag(op, ia32_op_tag);
7288  ia32_init_op(op, 1);
7289  op_ia32_CMovcc = op;
7290  op = new_ir_op(cur_opcode + iro_ia32_Call, "ia32_Call", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_call_attr_t));
7291  set_op_dump(op, ia32_dump_node);
7292  set_op_attrs_equal(op, ia32_call_attrs_equal);
7293  set_op_copy_attr(op, be_copy_attr);
7294  set_op_tag(op, ia32_op_tag);
7295  ia32_init_op(op, 4);
7296  op_ia32_Call = op;
7297  op = new_ir_op(cur_opcode + iro_ia32_ChangeCW, "ia32_ChangeCW", op_pin_state_pinned, irop_flag_constlike|irop_flag_dump_noblock, oparity_any, -1, sizeof(ia32_attr_t));
7298  set_op_dump(op, ia32_dump_node);
7299  set_op_attrs_equal(op, ia32_attrs_equal);
7300  set_op_copy_attr(op, be_copy_attr);
7301  set_op_tag(op, ia32_op_tag);
7302  ia32_init_op(op, 3);
7303  op_ia32_ChangeCW = op;
7304  op = new_ir_op(cur_opcode + iro_ia32_Cltd, "ia32_Cltd", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7305  set_op_dump(op, ia32_dump_node);
7306  set_op_attrs_equal(op, ia32_attrs_equal);
7307  set_op_copy_attr(op, be_copy_attr);
7308  set_op_tag(op, ia32_op_tag);
7309  ia32_init_op(op, 1);
7310  op_ia32_Cltd = op;
7311  op = new_ir_op(cur_opcode + iro_ia32_Cmc, "ia32_Cmc", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_condcode_attr_t));
7312  set_op_dump(op, ia32_dump_node);
7313  set_op_attrs_equal(op, ia32_condcode_attrs_equal);
7314  set_op_copy_attr(op, be_copy_attr);
7315  set_op_tag(op, ia32_op_tag);
7316  ia32_init_op(op, 1);
7317  op_ia32_Cmc = op;
7318  op = new_ir_op(cur_opcode + iro_ia32_Cmp, "ia32_Cmp", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7319  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7320  set_op_attrs_equal(op, ia32_attrs_equal);
7321  set_op_copy_attr(op, be_copy_attr);
7322  set_op_tag(op, ia32_op_tag);
7323  ia32_init_op(op, 1);
7324  op_ia32_Cmp = op;
7325  op = new_ir_op(cur_opcode + iro_ia32_CmpXChgMem, "ia32_CmpXChgMem", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7326  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7327  set_op_attrs_equal(op, ia32_attrs_equal);
7328  set_op_copy_attr(op, be_copy_attr);
7329  set_op_tag(op, ia32_op_tag);
7330  ia32_init_op(op, 2);
7331  op_ia32_CmpXChgMem = op;
7332  op = new_ir_op(cur_opcode + iro_ia32_Const, "ia32_Const", op_pin_state_floats, irop_flag_constlike, oparity_any, -1, sizeof(ia32_immediate_attr_t));
7333  set_op_dump(op, ia32_dump_node);
7334  set_op_attrs_equal(op, ia32_immediate_attrs_equal);
7335  set_op_copy_attr(op, be_copy_attr);
7336  set_op_tag(op, ia32_op_tag);
7337  ia32_init_op(op, 1);
7338  op_ia32_Const = op;
7339  op = new_ir_op(cur_opcode + iro_ia32_Conv_FP2FP, "ia32_Conv_FP2FP", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7340  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7341  set_op_attrs_equal(op, ia32_attrs_equal);
7342  set_op_copy_attr(op, be_copy_attr);
7343  set_op_tag(op, ia32_op_tag);
7344  ia32_init_op(op, 8);
7345  op_ia32_Conv_FP2FP = op;
7346  op = new_ir_op(cur_opcode + iro_ia32_Conv_FP2I, "ia32_Conv_FP2I", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7347  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7348  set_op_attrs_equal(op, ia32_attrs_equal);
7349  set_op_copy_attr(op, be_copy_attr);
7350  set_op_tag(op, ia32_op_tag);
7351  ia32_init_op(op, 10);
7352  op_ia32_Conv_FP2I = op;
7353  op = new_ir_op(cur_opcode + iro_ia32_Conv_I2FP, "ia32_Conv_I2FP", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7354  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7355  set_op_attrs_equal(op, ia32_attrs_equal);
7356  set_op_copy_attr(op, be_copy_attr);
7357  set_op_tag(op, ia32_op_tag);
7358  ia32_init_op(op, 10);
7359  op_ia32_Conv_I2FP = op;
7360  op = new_ir_op(cur_opcode + iro_ia32_Conv_I2I, "ia32_Conv_I2I", op_pin_state_exc_pinned, irop_flag_fragile|irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7361  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7362  set_op_attrs_equal(op, ia32_attrs_equal);
7363  set_op_copy_attr(op, be_copy_attr);
7364  ir_op_set_memory_index(op, n_ia32_Conv_I2I_mem);
7365  ir_op_set_fragile_indices(op, pn_ia32_Conv_I2I_X_regular, pn_ia32_Conv_I2I_X_except);
7366  set_op_tag(op, ia32_op_tag);
7367  ia32_init_op(op, 1);
7368  op_ia32_Conv_I2I = op;
7369  op = new_ir_op(cur_opcode + iro_ia32_CopyB, "ia32_CopyB", op_pin_state_floats, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_copyb_attr_t));
7370  ir_op_set_memory_index(op, 3); set_op_dump(op, ia32_dump_node);
7371  set_op_attrs_equal(op, ia32_copyb_attrs_equal);
7372  set_op_copy_attr(op, be_copy_attr);
7373  set_op_tag(op, ia32_op_tag);
7374  ia32_init_op(op, 250);
7375  op_ia32_CopyB = op;
7376  op = new_ir_op(cur_opcode + iro_ia32_CopyB_i, "ia32_CopyB_i", op_pin_state_floats, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_copyb_attr_t));
7377  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7378  set_op_attrs_equal(op, ia32_copyb_attrs_equal);
7379  set_op_copy_attr(op, be_copy_attr);
7380  set_op_tag(op, ia32_op_tag);
7381  ia32_init_op(op, 3);
7382  op_ia32_CopyB_i = op;
7383  op = new_ir_op(cur_opcode + iro_ia32_CopyEbpEsp, "ia32_CopyEbpEsp", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7384  set_op_dump(op, ia32_dump_node);
7385  set_op_attrs_equal(op, ia32_attrs_equal);
7386  set_op_copy_attr(op, be_copy_attr);
7387  set_op_tag(op, ia32_op_tag);
7388  ia32_init_op(op, 1);
7389  op_ia32_CopyEbpEsp = op;
7390  op = new_ir_op(cur_opcode + iro_ia32_CvtSI2SD, "ia32_CvtSI2SD", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7391  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7392  set_op_attrs_equal(op, ia32_attrs_equal);
7393  set_op_copy_attr(op, be_copy_attr);
7394  set_op_tag(op, ia32_op_tag);
7395  ia32_init_op(op, 2);
7396  op_ia32_CvtSI2SD = op;
7397  op = new_ir_op(cur_opcode + iro_ia32_CvtSI2SS, "ia32_CvtSI2SS", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7398  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7399  set_op_attrs_equal(op, ia32_attrs_equal);
7400  set_op_copy_attr(op, be_copy_attr);
7401  set_op_tag(op, ia32_op_tag);
7402  ia32_init_op(op, 2);
7403  op_ia32_CvtSI2SS = op;
7404  op = new_ir_op(cur_opcode + iro_ia32_Cwtl, "ia32_Cwtl", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7405  set_op_dump(op, ia32_dump_node);
7406  set_op_attrs_equal(op, ia32_attrs_equal);
7407  set_op_copy_attr(op, be_copy_attr);
7408  set_op_tag(op, ia32_op_tag);
7409  ia32_init_op(op, 1);
7410  op_ia32_Cwtl = op;
7411  op = new_ir_op(cur_opcode + iro_ia32_Dec, "ia32_Dec", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7412  set_op_dump(op, ia32_dump_node);
7413  set_op_attrs_equal(op, ia32_attrs_equal);
7414  set_op_copy_attr(op, be_copy_attr);
7415  set_op_tag(op, ia32_op_tag);
7416  ia32_init_op(op, 1);
7417  op_ia32_Dec = op;
7418  op = new_ir_op(cur_opcode + iro_ia32_DecMem, "ia32_DecMem", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7419  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7420  set_op_attrs_equal(op, ia32_attrs_equal);
7421  set_op_copy_attr(op, be_copy_attr);
7422  set_op_tag(op, ia32_op_tag);
7423  ia32_init_op(op, 1);
7424  op_ia32_DecMem = op;
7425  op = new_ir_op(cur_opcode + iro_ia32_Div, "ia32_Div", op_pin_state_exc_pinned, irop_flag_fragile|irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7426  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7427  set_op_attrs_equal(op, ia32_attrs_equal);
7428  set_op_copy_attr(op, be_copy_attr);
7429  ir_op_set_memory_index(op, n_ia32_Div_mem);
7430  ir_op_set_fragile_indices(op, pn_ia32_Div_X_regular, pn_ia32_Div_X_except);
7431  set_op_tag(op, ia32_op_tag);
7432  ia32_init_op(op, 25);
7433  op_ia32_Div = op;
7434  op = new_ir_op(cur_opcode + iro_ia32_Divs, "ia32_Divs", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7435  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7436  set_op_attrs_equal(op, ia32_attrs_equal);
7437  set_op_copy_attr(op, be_copy_attr);
7438  set_op_tag(op, ia32_op_tag);
7439  ia32_init_op(op, 16);
7440  op_ia32_Divs = op;
7441  op = new_ir_op(cur_opcode + iro_ia32_Enter, "ia32_Enter", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7442  set_op_dump(op, ia32_dump_node);
7443  set_op_attrs_equal(op, ia32_attrs_equal);
7444  set_op_copy_attr(op, be_copy_attr);
7445  set_op_tag(op, ia32_op_tag);
7446  ia32_init_op(op, 15);
7447  op_ia32_Enter = op;
7448  op = new_ir_op(cur_opcode + iro_ia32_FldCW, "ia32_FldCW", op_pin_state_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7449  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7450  set_op_attrs_equal(op, ia32_attrs_equal);
7451  set_op_copy_attr(op, be_copy_attr);
7452  set_op_tag(op, ia32_op_tag);
7453  ia32_init_op(op, 5);
7454  op_ia32_FldCW = op;
7455  op = new_ir_op(cur_opcode + iro_ia32_FnstCW, "ia32_FnstCW", op_pin_state_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7456  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7457  set_op_attrs_equal(op, ia32_attrs_equal);
7458  set_op_copy_attr(op, be_copy_attr);
7459  set_op_tag(op, ia32_op_tag);
7460  ia32_init_op(op, 5);
7461  op_ia32_FnstCW = op;
7462  op = new_ir_op(cur_opcode + iro_ia32_FnstCWNOP, "ia32_FnstCWNOP", op_pin_state_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7463  set_op_dump(op, ia32_dump_node);
7464  set_op_attrs_equal(op, ia32_attrs_equal);
7465  set_op_copy_attr(op, be_copy_attr);
7466  set_op_tag(op, ia32_op_tag);
7467  ia32_init_op(op, 0);
7468  op_ia32_FnstCWNOP = op;
7469  op = new_ir_op(cur_opcode + iro_ia32_FtstFnstsw, "ia32_FtstFnstsw", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7470  set_op_dump(op, ia32_dump_node);
7471  set_op_attrs_equal(op, ia32_attrs_equal);
7472  set_op_copy_attr(op, be_copy_attr);
7473  set_op_tag(op, ia32_op_tag);
7474  ia32_init_op(op, 3);
7475  op_ia32_FtstFnstsw = op;
7476  op = new_ir_op(cur_opcode + iro_ia32_FucomFnstsw, "ia32_FucomFnstsw", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_x87_attr_t));
7477  set_op_dump(op, ia32_dump_node);
7478  set_op_attrs_equal(op, ia32_x87_attrs_equal);
7479  set_op_copy_attr(op, be_copy_attr);
7480  set_op_tag(op, ia32_op_tag);
7481  ia32_init_op(op, 3);
7482  op_ia32_FucomFnstsw = op;
7483  op = new_ir_op(cur_opcode + iro_ia32_Fucomi, "ia32_Fucomi", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_x87_attr_t));
7484  set_op_dump(op, ia32_dump_node);
7485  set_op_attrs_equal(op, ia32_x87_attrs_equal);
7486  set_op_copy_attr(op, be_copy_attr);
7487  set_op_tag(op, ia32_op_tag);
7488  ia32_init_op(op, 3);
7489  op_ia32_Fucomi = op;
7490  op = new_ir_op(cur_opcode + iro_ia32_FucomppFnstsw, "ia32_FucomppFnstsw", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_x87_attr_t));
7491  set_op_dump(op, ia32_dump_node);
7492  set_op_attrs_equal(op, ia32_x87_attrs_equal);
7493  set_op_copy_attr(op, be_copy_attr);
7494  set_op_tag(op, ia32_op_tag);
7495  ia32_init_op(op, 3);
7496  op_ia32_FucomppFnstsw = op;
7497  op = new_ir_op(cur_opcode + iro_ia32_GetEIP, "ia32_GetEIP", op_pin_state_floats, irop_flag_constlike, oparity_any, -1, sizeof(ia32_attr_t));
7498  set_op_dump(op, ia32_dump_node);
7499  set_op_attrs_equal(op, ia32_attrs_equal);
7500  set_op_copy_attr(op, be_copy_attr);
7501  set_op_tag(op, ia32_op_tag);
7502  ia32_init_op(op, 5);
7503  op_ia32_GetEIP = op;
7504  op = new_ir_op(cur_opcode + iro_ia32_IDiv, "ia32_IDiv", op_pin_state_exc_pinned, irop_flag_fragile|irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7505  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7506  set_op_attrs_equal(op, ia32_attrs_equal);
7507  set_op_copy_attr(op, be_copy_attr);
7508  ir_op_set_memory_index(op, n_ia32_IDiv_mem);
7509  ir_op_set_fragile_indices(op, pn_ia32_IDiv_X_regular, pn_ia32_IDiv_X_except);
7510  set_op_tag(op, ia32_op_tag);
7511  ia32_init_op(op, 25);
7512  op_ia32_IDiv = op;
7513  op = new_ir_op(cur_opcode + iro_ia32_IJmp, "ia32_IJmp", op_pin_state_pinned, irop_flag_cfopcode|irop_flag_unknown_jump|irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7514  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7515  set_op_attrs_equal(op, ia32_attrs_equal);
7516  set_op_copy_attr(op, be_copy_attr);
7517  set_op_tag(op, ia32_op_tag);
7518  ia32_init_op(op, 1);
7519  op_ia32_IJmp = op;
7520  op = new_ir_op(cur_opcode + iro_ia32_IMul, "ia32_IMul", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7521  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7522  set_op_attrs_equal(op, ia32_attrs_equal);
7523  set_op_copy_attr(op, be_copy_attr);
7524  set_op_tag(op, ia32_op_tag);
7525  ia32_init_op(op, 5);
7526  op_ia32_IMul = op;
7527  op = new_ir_op(cur_opcode + iro_ia32_IMul1OP, "ia32_IMul1OP", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7528  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7529  set_op_attrs_equal(op, ia32_attrs_equal);
7530  set_op_copy_attr(op, be_copy_attr);
7531  set_op_tag(op, ia32_op_tag);
7532  ia32_init_op(op, 5);
7533  op_ia32_IMul1OP = op;
7534  op = new_ir_op(cur_opcode + iro_ia32_IMulImm, "ia32_IMulImm", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7535  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7536  set_op_attrs_equal(op, ia32_attrs_equal);
7537  set_op_copy_attr(op, be_copy_attr);
7538  set_op_tag(op, ia32_op_tag);
7539  ia32_init_op(op, 5);
7540  op_ia32_IMulImm = op;
7541  op = new_ir_op(cur_opcode + iro_ia32_Immediate, "ia32_Immediate", op_pin_state_pinned, irop_flag_constlike, oparity_any, -1, sizeof(ia32_immediate_attr_t));
7542  set_op_dump(op, ia32_dump_node);
7543  set_op_attrs_equal(op, ia32_immediate_attrs_equal);
7544  set_op_copy_attr(op, be_copy_attr);
7545  set_op_hash(op, ia32_hash_Immediate);
7546  set_op_tag(op, ia32_op_tag);
7547  ia32_init_op(op, 0);
7548  op_ia32_Immediate = op;
7549  op = new_ir_op(cur_opcode + iro_ia32_Inc, "ia32_Inc", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7550  set_op_dump(op, ia32_dump_node);
7551  set_op_attrs_equal(op, ia32_attrs_equal);
7552  set_op_copy_attr(op, be_copy_attr);
7553  set_op_tag(op, ia32_op_tag);
7554  ia32_init_op(op, 1);
7555  op_ia32_Inc = op;
7556  op = new_ir_op(cur_opcode + iro_ia32_IncMem, "ia32_IncMem", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7557  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7558  set_op_attrs_equal(op, ia32_attrs_equal);
7559  set_op_copy_attr(op, be_copy_attr);
7560  set_op_tag(op, ia32_op_tag);
7561  ia32_init_op(op, 1);
7562  op_ia32_IncMem = op;
7563  op = new_ir_op(cur_opcode + iro_ia32_Inport, "ia32_Inport", op_pin_state_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7564  ir_op_set_memory_index(op, 1); set_op_dump(op, ia32_dump_node);
7565  set_op_attrs_equal(op, ia32_attrs_equal);
7566  set_op_copy_attr(op, be_copy_attr);
7567  set_op_tag(op, ia32_op_tag);
7568  ia32_init_op(op, 1);
7569  op_ia32_Inport = op;
7570  op = new_ir_op(cur_opcode + iro_ia32_Jcc, "ia32_Jcc", op_pin_state_pinned, irop_flag_cfopcode|irop_flag_forking, oparity_any, -1, sizeof(ia32_condcode_attr_t));
7571  set_op_dump(op, ia32_dump_node);
7572  set_op_attrs_equal(op, ia32_condcode_attrs_equal);
7573  set_op_copy_attr(op, be_copy_attr);
7574  set_op_tag(op, ia32_op_tag);
7575  ia32_init_op(op, 2);
7576  op_ia32_Jcc = op;
7577  op = new_ir_op(cur_opcode + iro_ia32_Jmp, "ia32_Jmp", op_pin_state_pinned, irop_flag_cfopcode, oparity_any, -1, sizeof(ia32_attr_t));
7578  set_op_dump(op, ia32_dump_node);
7579  set_op_attrs_equal(op, ia32_attrs_equal);
7580  set_op_copy_attr(op, be_copy_attr);
7581  set_op_tag(op, ia32_op_tag);
7582  ia32_init_op(op, 1);
7583  op_ia32_Jmp = op;
7584  op = new_ir_op(cur_opcode + iro_ia32_LdTls, "ia32_LdTls", op_pin_state_floats, irop_flag_constlike, oparity_any, -1, sizeof(ia32_attr_t));
7585  set_op_dump(op, ia32_dump_node);
7586  set_op_attrs_equal(op, ia32_attrs_equal);
7587  set_op_copy_attr(op, be_copy_attr);
7588  set_op_tag(op, ia32_op_tag);
7589  ia32_init_op(op, 1);
7590  op_ia32_LdTls = op;
7591  op = new_ir_op(cur_opcode + iro_ia32_Lea, "ia32_Lea", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7592  set_op_dump(op, ia32_dump_node);
7593  set_op_attrs_equal(op, ia32_attrs_equal);
7594  set_op_copy_attr(op, be_copy_attr);
7595  set_op_tag(op, ia32_op_tag);
7596  ia32_init_op(op, 2);
7597  op_ia32_Lea = op;
7598  op = new_ir_op(cur_opcode + iro_ia32_Leave, "ia32_Leave", op_pin_state_floats, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7599  ir_op_set_memory_index(op, 0); set_op_dump(op, ia32_dump_node);
7600  set_op_attrs_equal(op, ia32_attrs_equal);
7601  set_op_copy_attr(op, be_copy_attr);
7602  set_op_tag(op, ia32_op_tag);
7603  ia32_init_op(op, 3);
7604  op_ia32_Leave = op;
7605  op = new_ir_op(cur_opcode + iro_ia32_Load, "ia32_Load", op_pin_state_exc_pinned, irop_flag_fragile|irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7606  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7607  set_op_attrs_equal(op, ia32_attrs_equal);
7608  set_op_copy_attr(op, be_copy_attr);
7609  ir_op_set_memory_index(op, n_ia32_Load_mem);
7610  ir_op_set_fragile_indices(op, pn_ia32_Load_X_regular, pn_ia32_Load_X_except);
7611  set_op_tag(op, ia32_op_tag);
7612  ia32_init_op(op, 0);
7613  op_ia32_Load = op;
7614  op = new_ir_op(cur_opcode + iro_ia32_Maxs, "ia32_Maxs", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7615  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7616  set_op_attrs_equal(op, ia32_attrs_equal);
7617  set_op_copy_attr(op, be_copy_attr);
7618  set_op_tag(op, ia32_op_tag);
7619  ia32_init_op(op, 2);
7620  op_ia32_Maxs = op;
7621  op = new_ir_op(cur_opcode + iro_ia32_Mins, "ia32_Mins", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7622  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7623  set_op_attrs_equal(op, ia32_attrs_equal);
7624  set_op_copy_attr(op, be_copy_attr);
7625  set_op_tag(op, ia32_op_tag);
7626  ia32_init_op(op, 2);
7627  op_ia32_Mins = op;
7628  op = new_ir_op(cur_opcode + iro_ia32_Minus64, "ia32_Minus64", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7629  set_op_dump(op, ia32_dump_node);
7630  set_op_attrs_equal(op, ia32_attrs_equal);
7631  set_op_copy_attr(op, be_copy_attr);
7632  set_op_tag(op, ia32_op_tag);
7633  ia32_init_op(op, 3);
7634  op_ia32_Minus64 = op;
7635  op = new_ir_op(cur_opcode + iro_ia32_Movd, "ia32_Movd", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7636  set_op_dump(op, ia32_dump_node);
7637  set_op_attrs_equal(op, ia32_attrs_equal);
7638  set_op_copy_attr(op, be_copy_attr);
7639  set_op_tag(op, ia32_op_tag);
7640  ia32_init_op(op, 1);
7641  op_ia32_Movd = op;
7642  op = new_ir_op(cur_opcode + iro_ia32_Mul, "ia32_Mul", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7643  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7644  set_op_attrs_equal(op, ia32_attrs_equal);
7645  set_op_copy_attr(op, be_copy_attr);
7646  set_op_tag(op, ia32_op_tag);
7647  ia32_init_op(op, 10);
7648  op_ia32_Mul = op;
7649  op = new_ir_op(cur_opcode + iro_ia32_Muls, "ia32_Muls", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7650  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7651  set_op_attrs_equal(op, ia32_attrs_equal);
7652  set_op_copy_attr(op, be_copy_attr);
7653  set_op_tag(op, ia32_op_tag);
7654  ia32_init_op(op, 4);
7655  op_ia32_Muls = op;
7656  op = new_ir_op(cur_opcode + iro_ia32_Neg, "ia32_Neg", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7657  set_op_dump(op, ia32_dump_node);
7658  set_op_attrs_equal(op, ia32_attrs_equal);
7659  set_op_copy_attr(op, be_copy_attr);
7660  set_op_tag(op, ia32_op_tag);
7661  ia32_init_op(op, 1);
7662  op_ia32_Neg = op;
7663  op = new_ir_op(cur_opcode + iro_ia32_NegMem, "ia32_NegMem", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7664  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7665  set_op_attrs_equal(op, ia32_attrs_equal);
7666  set_op_copy_attr(op, be_copy_attr);
7667  set_op_tag(op, ia32_op_tag);
7668  ia32_init_op(op, 1);
7669  op_ia32_NegMem = op;
7670  op = new_ir_op(cur_opcode + iro_ia32_NoReg_FP, "ia32_NoReg_FP", op_pin_state_pinned, irop_flag_constlike|irop_flag_dump_noblock, oparity_any, -1, sizeof(ia32_attr_t));
7671  set_op_dump(op, ia32_dump_node);
7672  set_op_attrs_equal(op, ia32_attrs_equal);
7673  set_op_copy_attr(op, be_copy_attr);
7674  set_op_tag(op, ia32_op_tag);
7675  ia32_init_op(op, 0);
7676  op_ia32_NoReg_FP = op;
7677  op = new_ir_op(cur_opcode + iro_ia32_NoReg_GP, "ia32_NoReg_GP", op_pin_state_pinned, irop_flag_constlike|irop_flag_dump_noblock, oparity_any, -1, sizeof(ia32_attr_t));
7678  set_op_dump(op, ia32_dump_node);
7679  set_op_attrs_equal(op, ia32_attrs_equal);
7680  set_op_copy_attr(op, be_copy_attr);
7681  set_op_tag(op, ia32_op_tag);
7682  ia32_init_op(op, 0);
7683  op_ia32_NoReg_GP = op;
7684  op = new_ir_op(cur_opcode + iro_ia32_NoReg_XMM, "ia32_NoReg_XMM", op_pin_state_pinned, irop_flag_constlike|irop_flag_dump_noblock, oparity_any, -1, sizeof(ia32_attr_t));
7685  set_op_dump(op, ia32_dump_node);
7686  set_op_attrs_equal(op, ia32_attrs_equal);
7687  set_op_copy_attr(op, be_copy_attr);
7688  set_op_tag(op, ia32_op_tag);
7689  ia32_init_op(op, 0);
7690  op_ia32_NoReg_XMM = op;
7691  op = new_ir_op(cur_opcode + iro_ia32_Not, "ia32_Not", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7692  set_op_dump(op, ia32_dump_node);
7693  set_op_attrs_equal(op, ia32_attrs_equal);
7694  set_op_copy_attr(op, be_copy_attr);
7695  set_op_tag(op, ia32_op_tag);
7696  ia32_init_op(op, 1);
7697  op_ia32_Not = op;
7698  op = new_ir_op(cur_opcode + iro_ia32_NotMem, "ia32_NotMem", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7699  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7700  set_op_attrs_equal(op, ia32_attrs_equal);
7701  set_op_copy_attr(op, be_copy_attr);
7702  set_op_tag(op, ia32_op_tag);
7703  ia32_init_op(op, 1);
7704  op_ia32_NotMem = op;
7705  op = new_ir_op(cur_opcode + iro_ia32_Or, "ia32_Or", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7706  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7707  set_op_attrs_equal(op, ia32_attrs_equal);
7708  set_op_copy_attr(op, be_copy_attr);
7709  set_op_tag(op, ia32_op_tag);
7710  ia32_init_op(op, 1);
7711  op_ia32_Or = op;
7712  op = new_ir_op(cur_opcode + iro_ia32_OrMem, "ia32_OrMem", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7713  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7714  set_op_attrs_equal(op, ia32_attrs_equal);
7715  set_op_copy_attr(op, be_copy_attr);
7716  set_op_tag(op, ia32_op_tag);
7717  ia32_init_op(op, 1);
7718  op_ia32_OrMem = op;
7719  op = new_ir_op(cur_opcode + iro_ia32_Orp, "ia32_Orp", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7720  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7721  set_op_attrs_equal(op, ia32_attrs_equal);
7722  set_op_copy_attr(op, be_copy_attr);
7723  set_op_tag(op, ia32_op_tag);
7724  ia32_init_op(op, 3);
7725  op_ia32_Orp = op;
7726  op = new_ir_op(cur_opcode + iro_ia32_Outport, "ia32_Outport", op_pin_state_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7727  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7728  set_op_attrs_equal(op, ia32_attrs_equal);
7729  set_op_copy_attr(op, be_copy_attr);
7730  set_op_tag(op, ia32_op_tag);
7731  ia32_init_op(op, 1);
7732  op_ia32_Outport = op;
7733  op = new_ir_op(cur_opcode + iro_ia32_Pop, "ia32_Pop", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7734  ir_op_set_memory_index(op, 0); set_op_dump(op, ia32_dump_node);
7735  set_op_attrs_equal(op, ia32_attrs_equal);
7736  set_op_copy_attr(op, be_copy_attr);
7737  set_op_tag(op, ia32_op_tag);
7738  ia32_init_op(op, 3);
7739  op_ia32_Pop = op;
7740  op = new_ir_op(cur_opcode + iro_ia32_PopMem, "ia32_PopMem", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7741  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7742  set_op_attrs_equal(op, ia32_attrs_equal);
7743  set_op_copy_attr(op, be_copy_attr);
7744  set_op_tag(op, ia32_op_tag);
7745  ia32_init_op(op, 3);
7746  op_ia32_PopMem = op;
7747  op = new_ir_op(cur_opcode + iro_ia32_Popcnt, "ia32_Popcnt", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7748  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7749  set_op_attrs_equal(op, ia32_attrs_equal);
7750  set_op_copy_attr(op, be_copy_attr);
7751  set_op_tag(op, ia32_op_tag);
7752  ia32_init_op(op, 1);
7753  op_ia32_Popcnt = op;
7754  op = new_ir_op(cur_opcode + iro_ia32_Prefetch, "ia32_Prefetch", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7755  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7756  set_op_attrs_equal(op, ia32_attrs_equal);
7757  set_op_copy_attr(op, be_copy_attr);
7758  set_op_tag(op, ia32_op_tag);
7759  ia32_init_op(op, 0);
7760  op_ia32_Prefetch = op;
7761  op = new_ir_op(cur_opcode + iro_ia32_PrefetchNTA, "ia32_PrefetchNTA", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7762  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7763  set_op_attrs_equal(op, ia32_attrs_equal);
7764  set_op_copy_attr(op, be_copy_attr);
7765  set_op_tag(op, ia32_op_tag);
7766  ia32_init_op(op, 0);
7767  op_ia32_PrefetchNTA = op;
7768  op = new_ir_op(cur_opcode + iro_ia32_PrefetchT0, "ia32_PrefetchT0", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7769  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7770  set_op_attrs_equal(op, ia32_attrs_equal);
7771  set_op_copy_attr(op, be_copy_attr);
7772  set_op_tag(op, ia32_op_tag);
7773  ia32_init_op(op, 0);
7774  op_ia32_PrefetchT0 = op;
7775  op = new_ir_op(cur_opcode + iro_ia32_PrefetchT1, "ia32_PrefetchT1", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7776  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7777  set_op_attrs_equal(op, ia32_attrs_equal);
7778  set_op_copy_attr(op, be_copy_attr);
7779  set_op_tag(op, ia32_op_tag);
7780  ia32_init_op(op, 0);
7781  op_ia32_PrefetchT1 = op;
7782  op = new_ir_op(cur_opcode + iro_ia32_PrefetchT2, "ia32_PrefetchT2", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7783  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7784  set_op_attrs_equal(op, ia32_attrs_equal);
7785  set_op_copy_attr(op, be_copy_attr);
7786  set_op_tag(op, ia32_op_tag);
7787  ia32_init_op(op, 0);
7788  op_ia32_PrefetchT2 = op;
7789  op = new_ir_op(cur_opcode + iro_ia32_PrefetchW, "ia32_PrefetchW", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7790  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7791  set_op_attrs_equal(op, ia32_attrs_equal);
7792  set_op_copy_attr(op, be_copy_attr);
7793  set_op_tag(op, ia32_op_tag);
7794  ia32_init_op(op, 0);
7795  op_ia32_PrefetchW = op;
7796  op = new_ir_op(cur_opcode + iro_ia32_Pslld, "ia32_Pslld", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7797  set_op_dump(op, ia32_dump_node);
7798  set_op_attrs_equal(op, ia32_attrs_equal);
7799  set_op_copy_attr(op, be_copy_attr);
7800  set_op_tag(op, ia32_op_tag);
7801  ia32_init_op(op, 3);
7802  op_ia32_Pslld = op;
7803  op = new_ir_op(cur_opcode + iro_ia32_Psllq, "ia32_Psllq", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7804  set_op_dump(op, ia32_dump_node);
7805  set_op_attrs_equal(op, ia32_attrs_equal);
7806  set_op_copy_attr(op, be_copy_attr);
7807  set_op_tag(op, ia32_op_tag);
7808  ia32_init_op(op, 3);
7809  op_ia32_Psllq = op;
7810  op = new_ir_op(cur_opcode + iro_ia32_Psrld, "ia32_Psrld", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7811  set_op_dump(op, ia32_dump_node);
7812  set_op_attrs_equal(op, ia32_attrs_equal);
7813  set_op_copy_attr(op, be_copy_attr);
7814  set_op_tag(op, ia32_op_tag);
7815  ia32_init_op(op, 1);
7816  op_ia32_Psrld = op;
7817  op = new_ir_op(cur_opcode + iro_ia32_Push, "ia32_Push", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7818  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7819  set_op_attrs_equal(op, ia32_attrs_equal);
7820  set_op_copy_attr(op, be_copy_attr);
7821  set_op_tag(op, ia32_op_tag);
7822  ia32_init_op(op, 2);
7823  op_ia32_Push = op;
7824  op = new_ir_op(cur_opcode + iro_ia32_PushEax, "ia32_PushEax", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7825  set_op_dump(op, ia32_dump_node);
7826  set_op_attrs_equal(op, ia32_attrs_equal);
7827  set_op_copy_attr(op, be_copy_attr);
7828  set_op_tag(op, ia32_op_tag);
7829  ia32_init_op(op, 2);
7830  op_ia32_PushEax = op;
7831  op = new_ir_op(cur_opcode + iro_ia32_Ret, "ia32_Ret", op_pin_state_pinned, irop_flag_cfopcode, oparity_any, -1, sizeof(ia32_return_attr_t));
7832  set_op_dump(op, ia32_dump_node);
7833  set_op_attrs_equal(op, ia32_return_attrs_equal);
7834  set_op_copy_attr(op, be_copy_attr);
7835  set_op_tag(op, ia32_op_tag);
7836  ia32_init_op(op, 0);
7837  op_ia32_Ret = op;
7838  op = new_ir_op(cur_opcode + iro_ia32_Rol, "ia32_Rol", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7839  set_op_dump(op, ia32_dump_node);
7840  set_op_attrs_equal(op, ia32_attrs_equal);
7841  set_op_copy_attr(op, be_copy_attr);
7842  set_op_tag(op, ia32_op_tag);
7843  ia32_init_op(op, 1);
7844  op_ia32_Rol = op;
7845  op = new_ir_op(cur_opcode + iro_ia32_RolMem, "ia32_RolMem", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7846  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7847  set_op_attrs_equal(op, ia32_attrs_equal);
7848  set_op_copy_attr(op, be_copy_attr);
7849  set_op_tag(op, ia32_op_tag);
7850  ia32_init_op(op, 1);
7851  op_ia32_RolMem = op;
7852  op = new_ir_op(cur_opcode + iro_ia32_Ror, "ia32_Ror", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7853  set_op_dump(op, ia32_dump_node);
7854  set_op_attrs_equal(op, ia32_attrs_equal);
7855  set_op_copy_attr(op, be_copy_attr);
7856  set_op_tag(op, ia32_op_tag);
7857  ia32_init_op(op, 1);
7858  op_ia32_Ror = op;
7859  op = new_ir_op(cur_opcode + iro_ia32_RorMem, "ia32_RorMem", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7860  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7861  set_op_attrs_equal(op, ia32_attrs_equal);
7862  set_op_copy_attr(op, be_copy_attr);
7863  set_op_tag(op, ia32_op_tag);
7864  ia32_init_op(op, 1);
7865  op_ia32_RorMem = op;
7866  op = new_ir_op(cur_opcode + iro_ia32_Sahf, "ia32_Sahf", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7867  set_op_dump(op, ia32_dump_node);
7868  set_op_attrs_equal(op, ia32_attrs_equal);
7869  set_op_copy_attr(op, be_copy_attr);
7870  set_op_tag(op, ia32_op_tag);
7871  ia32_init_op(op, 1);
7872  op_ia32_Sahf = op;
7873  op = new_ir_op(cur_opcode + iro_ia32_Sar, "ia32_Sar", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7874  set_op_dump(op, ia32_dump_node);
7875  set_op_attrs_equal(op, ia32_attrs_equal);
7876  set_op_copy_attr(op, be_copy_attr);
7877  set_op_tag(op, ia32_op_tag);
7878  ia32_init_op(op, 1);
7879  op_ia32_Sar = op;
7880  op = new_ir_op(cur_opcode + iro_ia32_SarMem, "ia32_SarMem", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7881  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7882  set_op_attrs_equal(op, ia32_attrs_equal);
7883  set_op_copy_attr(op, be_copy_attr);
7884  set_op_tag(op, ia32_op_tag);
7885  ia32_init_op(op, 1);
7886  op_ia32_SarMem = op;
7887  op = new_ir_op(cur_opcode + iro_ia32_Sbb, "ia32_Sbb", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_condcode_attr_t));
7888  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7889  set_op_attrs_equal(op, ia32_condcode_attrs_equal);
7890  set_op_copy_attr(op, be_copy_attr);
7891  set_op_tag(op, ia32_op_tag);
7892  ia32_init_op(op, 1);
7893  op_ia32_Sbb = op;
7894  op = new_ir_op(cur_opcode + iro_ia32_Sbb0, "ia32_Sbb0", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_condcode_attr_t));
7895  set_op_dump(op, ia32_dump_node);
7896  set_op_attrs_equal(op, ia32_condcode_attrs_equal);
7897  set_op_copy_attr(op, be_copy_attr);
7898  set_op_tag(op, ia32_op_tag);
7899  ia32_init_op(op, 1);
7900  op_ia32_Sbb0 = op;
7901  op = new_ir_op(cur_opcode + iro_ia32_Setcc, "ia32_Setcc", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_condcode_attr_t));
7902  set_op_dump(op, ia32_dump_node);
7903  set_op_attrs_equal(op, ia32_condcode_attrs_equal);
7904  set_op_copy_attr(op, be_copy_attr);
7905  set_op_tag(op, ia32_op_tag);
7906  ia32_init_op(op, 1);
7907  op_ia32_Setcc = op;
7908  op = new_ir_op(cur_opcode + iro_ia32_SetccMem, "ia32_SetccMem", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_condcode_attr_t));
7909  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7910  set_op_attrs_equal(op, ia32_condcode_attrs_equal);
7911  set_op_copy_attr(op, be_copy_attr);
7912  set_op_tag(op, ia32_op_tag);
7913  ia32_init_op(op, 1);
7914  op_ia32_SetccMem = op;
7915  op = new_ir_op(cur_opcode + iro_ia32_Shl, "ia32_Shl", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7916  set_op_dump(op, ia32_dump_node);
7917  set_op_attrs_equal(op, ia32_attrs_equal);
7918  set_op_copy_attr(op, be_copy_attr);
7919  set_op_tag(op, ia32_op_tag);
7920  ia32_init_op(op, 1);
7921  op_ia32_Shl = op;
7922  op = new_ir_op(cur_opcode + iro_ia32_ShlD, "ia32_ShlD", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7923  set_op_dump(op, ia32_dump_node);
7924  set_op_attrs_equal(op, ia32_attrs_equal);
7925  set_op_copy_attr(op, be_copy_attr);
7926  set_op_tag(op, ia32_op_tag);
7927  ia32_init_op(op, 6);
7928  op_ia32_ShlD = op;
7929  op = new_ir_op(cur_opcode + iro_ia32_ShlMem, "ia32_ShlMem", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7930  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7931  set_op_attrs_equal(op, ia32_attrs_equal);
7932  set_op_copy_attr(op, be_copy_attr);
7933  set_op_tag(op, ia32_op_tag);
7934  ia32_init_op(op, 1);
7935  op_ia32_ShlMem = op;
7936  op = new_ir_op(cur_opcode + iro_ia32_Shr, "ia32_Shr", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7937  set_op_dump(op, ia32_dump_node);
7938  set_op_attrs_equal(op, ia32_attrs_equal);
7939  set_op_copy_attr(op, be_copy_attr);
7940  set_op_tag(op, ia32_op_tag);
7941  ia32_init_op(op, 1);
7942  op_ia32_Shr = op;
7943  op = new_ir_op(cur_opcode + iro_ia32_ShrD, "ia32_ShrD", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7944  set_op_dump(op, ia32_dump_node);
7945  set_op_attrs_equal(op, ia32_attrs_equal);
7946  set_op_copy_attr(op, be_copy_attr);
7947  set_op_tag(op, ia32_op_tag);
7948  ia32_init_op(op, 6);
7949  op_ia32_ShrD = op;
7950  op = new_ir_op(cur_opcode + iro_ia32_ShrMem, "ia32_ShrMem", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7951  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7952  set_op_attrs_equal(op, ia32_attrs_equal);
7953  set_op_copy_attr(op, be_copy_attr);
7954  set_op_tag(op, ia32_op_tag);
7955  ia32_init_op(op, 1);
7956  op_ia32_ShrMem = op;
7957  op = new_ir_op(cur_opcode + iro_ia32_Stc, "ia32_Stc", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7958  set_op_dump(op, ia32_dump_node);
7959  set_op_attrs_equal(op, ia32_attrs_equal);
7960  set_op_copy_attr(op, be_copy_attr);
7961  set_op_tag(op, ia32_op_tag);
7962  ia32_init_op(op, 1);
7963  op_ia32_Stc = op;
7964  op = new_ir_op(cur_opcode + iro_ia32_Store, "ia32_Store", op_pin_state_exc_pinned, irop_flag_fragile|irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7965  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7966  set_op_attrs_equal(op, ia32_attrs_equal);
7967  set_op_copy_attr(op, be_copy_attr);
7968  ir_op_set_memory_index(op, n_ia32_Store_mem);
7969  ir_op_set_fragile_indices(op, pn_ia32_Store_X_regular, pn_ia32_Store_X_except);
7970  set_op_tag(op, ia32_op_tag);
7971  ia32_init_op(op, 2);
7972  op_ia32_Store = op;
7973  op = new_ir_op(cur_opcode + iro_ia32_Sub, "ia32_Sub", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7974  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7975  set_op_attrs_equal(op, ia32_attrs_equal);
7976  set_op_copy_attr(op, be_copy_attr);
7977  set_op_tag(op, ia32_op_tag);
7978  ia32_init_op(op, 1);
7979  op_ia32_Sub = op;
7980  op = new_ir_op(cur_opcode + iro_ia32_SubMem, "ia32_SubMem", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7981  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7982  set_op_attrs_equal(op, ia32_attrs_equal);
7983  set_op_copy_attr(op, be_copy_attr);
7984  set_op_tag(op, ia32_op_tag);
7985  ia32_init_op(op, 1);
7986  op_ia32_SubMem = op;
7987  op = new_ir_op(cur_opcode + iro_ia32_SubSP, "ia32_SubSP", op_pin_state_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7988  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7989  set_op_attrs_equal(op, ia32_attrs_equal);
7990  set_op_copy_attr(op, be_copy_attr);
7991  set_op_tag(op, ia32_op_tag);
7992  ia32_init_op(op, 2);
7993  op_ia32_SubSP = op;
7994  op = new_ir_op(cur_opcode + iro_ia32_Subs, "ia32_Subs", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7995  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
7996  set_op_attrs_equal(op, ia32_attrs_equal);
7997  set_op_copy_attr(op, be_copy_attr);
7998  set_op_tag(op, ia32_op_tag);
7999  ia32_init_op(op, 4);
8000  op_ia32_Subs = op;
8001  op = new_ir_op(cur_opcode + iro_ia32_SwitchJmp, "ia32_SwitchJmp", op_pin_state_pinned, irop_flag_cfopcode|irop_flag_forking, oparity_any, -1, sizeof(ia32_switch_attr_t));
8002  set_op_dump(op, ia32_dump_node);
8003  set_op_attrs_equal(op, ia32_switch_attrs_equal);
8004  set_op_copy_attr(op, be_copy_attr);
8005  set_op_tag(op, ia32_op_tag);
8006  ia32_init_op(op, 2);
8007  op_ia32_SwitchJmp = op;
8008  op = new_ir_op(cur_opcode + iro_ia32_Test, "ia32_Test", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
8009  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
8010  set_op_attrs_equal(op, ia32_attrs_equal);
8011  set_op_copy_attr(op, be_copy_attr);
8012  set_op_tag(op, ia32_op_tag);
8013  ia32_init_op(op, 1);
8014  op_ia32_Test = op;
8015  op = new_ir_op(cur_opcode + iro_ia32_UD2, "ia32_UD2", op_pin_state_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
8016  ir_op_set_memory_index(op, 0); set_op_dump(op, ia32_dump_node);
8017  set_op_attrs_equal(op, ia32_attrs_equal);
8018  set_op_copy_attr(op, be_copy_attr);
8019  set_op_tag(op, ia32_op_tag);
8020  ia32_init_op(op, 0);
8021  op_ia32_UD2 = op;
8022  op = new_ir_op(cur_opcode + iro_ia32_Ucomis, "ia32_Ucomis", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
8023  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
8024  set_op_attrs_equal(op, ia32_attrs_equal);
8025  set_op_copy_attr(op, be_copy_attr);
8026  set_op_tag(op, ia32_op_tag);
8027  ia32_init_op(op, 3);
8028  op_ia32_Ucomis = op;
8029  op = new_ir_op(cur_opcode + iro_ia32_Xor, "ia32_Xor", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
8030  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
8031  set_op_attrs_equal(op, ia32_attrs_equal);
8032  set_op_copy_attr(op, be_copy_attr);
8033  set_op_tag(op, ia32_op_tag);
8034  ia32_init_op(op, 1);
8035  op_ia32_Xor = op;
8036  op = new_ir_op(cur_opcode + iro_ia32_Xor0, "ia32_Xor0", op_pin_state_floats, irop_flag_constlike, oparity_any, -1, sizeof(ia32_attr_t));
8037  set_op_dump(op, ia32_dump_node);
8038  set_op_attrs_equal(op, ia32_attrs_equal);
8039  set_op_copy_attr(op, be_copy_attr);
8040  set_op_tag(op, ia32_op_tag);
8041  ia32_init_op(op, 1);
8042  op_ia32_Xor0 = op;
8043  op = new_ir_op(cur_opcode + iro_ia32_XorHighLow, "ia32_XorHighLow", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
8044  set_op_dump(op, ia32_dump_node);
8045  set_op_attrs_equal(op, ia32_attrs_equal);
8046  set_op_copy_attr(op, be_copy_attr);
8047  set_op_tag(op, ia32_op_tag);
8048  ia32_init_op(op, 1);
8049  op_ia32_XorHighLow = op;
8050  op = new_ir_op(cur_opcode + iro_ia32_XorMem, "ia32_XorMem", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
8051  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
8052  set_op_attrs_equal(op, ia32_attrs_equal);
8053  set_op_copy_attr(op, be_copy_attr);
8054  set_op_tag(op, ia32_op_tag);
8055  ia32_init_op(op, 1);
8056  op_ia32_XorMem = op;
8057  op = new_ir_op(cur_opcode + iro_ia32_Xorp, "ia32_Xorp", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
8058  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
8059  set_op_attrs_equal(op, ia32_attrs_equal);
8060  set_op_copy_attr(op, be_copy_attr);
8061  set_op_tag(op, ia32_op_tag);
8062  ia32_init_op(op, 3);
8063  op_ia32_Xorp = op;
8064  op = new_ir_op(cur_opcode + iro_ia32_emms, "ia32_emms", op_pin_state_floats, irop_flag_keep, oparity_any, -1, sizeof(ia32_attr_t));
8065  set_op_dump(op, ia32_dump_node);
8066  set_op_attrs_equal(op, attrs_equal_false);
8067  set_op_copy_attr(op, be_copy_attr);
8068  set_op_tag(op, ia32_op_tag);
8069  ia32_init_op(op, 3);
8070  op_ia32_emms = op;
8071  op = new_ir_op(cur_opcode + iro_ia32_fabs, "ia32_fabs", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
8072  set_op_dump(op, ia32_dump_node);
8073  set_op_attrs_equal(op, ia32_attrs_equal);
8074  set_op_copy_attr(op, be_copy_attr);
8075  set_op_tag(op, ia32_op_tag);
8076  ia32_init_op(op, 2);
8077  op_ia32_fabs = op;
8078  op = new_ir_op(cur_opcode + iro_ia32_fadd, "ia32_fadd", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_x87_attr_t));
8079  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
8080  set_op_attrs_equal(op, ia32_x87_attrs_equal);
8081  set_op_copy_attr(op, be_copy_attr);
8082  set_op_tag(op, ia32_op_tag);
8083  ia32_init_op(op, 4);
8084  op_ia32_fadd = op;
8085  op = new_ir_op(cur_opcode + iro_ia32_fchs, "ia32_fchs", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
8086  set_op_dump(op, ia32_dump_node);
8087  set_op_attrs_equal(op, ia32_attrs_equal);
8088  set_op_copy_attr(op, be_copy_attr);
8089  set_op_tag(op, ia32_op_tag);
8090  ia32_init_op(op, 2);
8091  op_ia32_fchs = op;
8092  op = new_ir_op(cur_opcode + iro_ia32_fdiv, "ia32_fdiv", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_x87_attr_t));
8093  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
8094  set_op_attrs_equal(op, ia32_x87_attrs_equal);
8095  set_op_copy_attr(op, be_copy_attr);
8096  set_op_tag(op, ia32_op_tag);
8097  ia32_init_op(op, 20);
8098  op_ia32_fdiv = op;
8099  op = new_ir_op(cur_opcode + iro_ia32_fdup, "ia32_fdup", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_x87_attr_t));
8100  set_op_dump(op, ia32_dump_node);
8101  set_op_attrs_equal(op, attrs_equal_false);
8102  set_op_copy_attr(op, be_copy_attr);
8103  set_op_tag(op, ia32_op_tag);
8104  ia32_init_op(op, 1);
8105  op_ia32_fdup = op;
8106  op = new_ir_op(cur_opcode + iro_ia32_femms, "ia32_femms", op_pin_state_floats, irop_flag_keep, oparity_any, -1, sizeof(ia32_attr_t));
8107  set_op_dump(op, ia32_dump_node);
8108  set_op_attrs_equal(op, attrs_equal_false);
8109  set_op_copy_attr(op, be_copy_attr);
8110  set_op_tag(op, ia32_op_tag);
8111  ia32_init_op(op, 3);
8112  op_ia32_femms = op;
8113  op = new_ir_op(cur_opcode + iro_ia32_ffreep, "ia32_ffreep", op_pin_state_floats, irop_flag_keep, oparity_any, -1, sizeof(ia32_x87_attr_t));
8114  set_op_dump(op, ia32_dump_node);
8115  set_op_attrs_equal(op, attrs_equal_false);
8116  set_op_copy_attr(op, be_copy_attr);
8117  set_op_tag(op, ia32_op_tag);
8118  ia32_init_op(op, 1);
8119  op_ia32_ffreep = op;
8120  op = new_ir_op(cur_opcode + iro_ia32_fild, "ia32_fild", op_pin_state_exc_pinned, irop_flag_fragile|irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
8121  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
8122  set_op_attrs_equal(op, ia32_attrs_equal);
8123  set_op_copy_attr(op, be_copy_attr);
8124  ir_op_set_memory_index(op, n_ia32_fild_mem);
8125  ir_op_set_fragile_indices(op, pn_ia32_fild_X_regular, pn_ia32_fild_X_except);
8126  set_op_tag(op, ia32_op_tag);
8127  ia32_init_op(op, 4);
8128  op_ia32_fild = op;
8129  op = new_ir_op(cur_opcode + iro_ia32_fist, "ia32_fist", op_pin_state_exc_pinned, irop_flag_fragile|irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_x87_attr_t));
8130  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
8131  set_op_attrs_equal(op, ia32_x87_attrs_equal);
8132  set_op_copy_attr(op, be_copy_attr);
8133  ir_op_set_memory_index(op, n_ia32_fist_mem);
8134  ir_op_set_fragile_indices(op, pn_ia32_fist_X_regular, pn_ia32_fist_X_except);
8135  set_op_tag(op, ia32_op_tag);
8136  ia32_init_op(op, 4);
8137  op_ia32_fist = op;
8138  op = new_ir_op(cur_opcode + iro_ia32_fistp, "ia32_fistp", op_pin_state_exc_pinned, irop_flag_fragile|irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_x87_attr_t));
8139  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
8140  set_op_attrs_equal(op, ia32_x87_attrs_equal);
8141  set_op_copy_attr(op, be_copy_attr);
8142  ir_op_set_memory_index(op, n_ia32_fistp_mem);
8143  ir_op_set_fragile_indices(op, pn_ia32_fistp_X_regular, pn_ia32_fistp_X_except);
8144  set_op_tag(op, ia32_op_tag);
8145  ia32_init_op(op, 4);
8146  op_ia32_fistp = op;
8147  op = new_ir_op(cur_opcode + iro_ia32_fisttp, "ia32_fisttp", op_pin_state_exc_pinned, irop_flag_fragile|irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_x87_attr_t));
8148  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
8149  set_op_attrs_equal(op, ia32_x87_attrs_equal);
8150  set_op_copy_attr(op, be_copy_attr);
8151  ir_op_set_memory_index(op, n_ia32_fisttp_mem);
8152  ir_op_set_fragile_indices(op, pn_ia32_fisttp_X_regular, pn_ia32_fisttp_X_except);
8153  set_op_tag(op, ia32_op_tag);
8154  ia32_init_op(op, 4);
8155  op_ia32_fisttp = op;
8156  op = new_ir_op(cur_opcode + iro_ia32_fld, "ia32_fld", op_pin_state_exc_pinned, irop_flag_fragile|irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
8157  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
8158  set_op_attrs_equal(op, ia32_attrs_equal);
8159  set_op_copy_attr(op, be_copy_attr);
8160  ir_op_set_memory_index(op, n_ia32_fld_mem);
8161  ir_op_set_fragile_indices(op, pn_ia32_fld_X_regular, pn_ia32_fld_X_except);
8162  set_op_tag(op, ia32_op_tag);
8163  ia32_init_op(op, 2);
8164  op_ia32_fld = op;
8165  op = new_ir_op(cur_opcode + iro_ia32_fld1, "ia32_fld1", op_pin_state_floats, irop_flag_constlike, oparity_any, -1, sizeof(ia32_attr_t));
8166  set_op_dump(op, ia32_dump_node);
8167  set_op_attrs_equal(op, ia32_attrs_equal);
8168  set_op_copy_attr(op, be_copy_attr);
8169  set_op_tag(op, ia32_op_tag);
8170  ia32_init_op(op, 4);
8171  op_ia32_fld1 = op;
8172  op = new_ir_op(cur_opcode + iro_ia32_fldl2e, "ia32_fldl2e", op_pin_state_floats, irop_flag_constlike, oparity_any, -1, sizeof(ia32_attr_t));
8173  set_op_dump(op, ia32_dump_node);
8174  set_op_attrs_equal(op, ia32_attrs_equal);
8175  set_op_copy_attr(op, be_copy_attr);
8176  set_op_tag(op, ia32_op_tag);
8177  ia32_init_op(op, 4);
8178  op_ia32_fldl2e = op;
8179  op = new_ir_op(cur_opcode + iro_ia32_fldl2t, "ia32_fldl2t", op_pin_state_floats, irop_flag_constlike, oparity_any, -1, sizeof(ia32_attr_t));
8180  set_op_dump(op, ia32_dump_node);
8181  set_op_attrs_equal(op, ia32_attrs_equal);
8182  set_op_copy_attr(op, be_copy_attr);
8183  set_op_tag(op, ia32_op_tag);
8184  ia32_init_op(op, 4);
8185  op_ia32_fldl2t = op;
8186  op = new_ir_op(cur_opcode + iro_ia32_fldlg2, "ia32_fldlg2", op_pin_state_floats, irop_flag_constlike, oparity_any, -1, sizeof(ia32_attr_t));
8187  set_op_dump(op, ia32_dump_node);
8188  set_op_attrs_equal(op, ia32_attrs_equal);
8189  set_op_copy_attr(op, be_copy_attr);
8190  set_op_tag(op, ia32_op_tag);
8191  ia32_init_op(op, 4);
8192  op_ia32_fldlg2 = op;
8193  op = new_ir_op(cur_opcode + iro_ia32_fldln2, "ia32_fldln2", op_pin_state_floats, irop_flag_constlike, oparity_any, -1, sizeof(ia32_attr_t));
8194  set_op_dump(op, ia32_dump_node);
8195  set_op_attrs_equal(op, ia32_attrs_equal);
8196  set_op_copy_attr(op, be_copy_attr);
8197  set_op_tag(op, ia32_op_tag);
8198  ia32_init_op(op, 4);
8199  op_ia32_fldln2 = op;
8200  op = new_ir_op(cur_opcode + iro_ia32_fldpi, "ia32_fldpi", op_pin_state_floats, irop_flag_constlike, oparity_any, -1, sizeof(ia32_attr_t));
8201  set_op_dump(op, ia32_dump_node);
8202  set_op_attrs_equal(op, ia32_attrs_equal);
8203  set_op_copy_attr(op, be_copy_attr);
8204  set_op_tag(op, ia32_op_tag);
8205  ia32_init_op(op, 4);
8206  op_ia32_fldpi = op;
8207  op = new_ir_op(cur_opcode + iro_ia32_fldz, "ia32_fldz", op_pin_state_floats, irop_flag_constlike, oparity_any, -1, sizeof(ia32_attr_t));
8208  set_op_dump(op, ia32_dump_node);
8209  set_op_attrs_equal(op, ia32_attrs_equal);
8210  set_op_copy_attr(op, be_copy_attr);
8211  set_op_tag(op, ia32_op_tag);
8212  ia32_init_op(op, 4);
8213  op_ia32_fldz = op;
8214  op = new_ir_op(cur_opcode + iro_ia32_fmul, "ia32_fmul", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_x87_attr_t));
8215  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
8216  set_op_attrs_equal(op, ia32_x87_attrs_equal);
8217  set_op_copy_attr(op, be_copy_attr);
8218  set_op_tag(op, ia32_op_tag);
8219  ia32_init_op(op, 4);
8220  op_ia32_fmul = op;
8221  op = new_ir_op(cur_opcode + iro_ia32_fpop, "ia32_fpop", op_pin_state_floats, irop_flag_keep, oparity_any, -1, sizeof(ia32_x87_attr_t));
8222  set_op_dump(op, ia32_dump_node);
8223  set_op_attrs_equal(op, attrs_equal_false);
8224  set_op_copy_attr(op, be_copy_attr);
8225  set_op_tag(op, ia32_op_tag);
8226  ia32_init_op(op, 1);
8227  op_ia32_fpop = op;
8228  op = new_ir_op(cur_opcode + iro_ia32_fst, "ia32_fst", op_pin_state_exc_pinned, irop_flag_fragile|irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_x87_attr_t));
8229  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
8230  set_op_attrs_equal(op, ia32_x87_attrs_equal);
8231  set_op_copy_attr(op, be_copy_attr);
8232  ir_op_set_memory_index(op, n_ia32_fst_mem);
8233  ir_op_set_fragile_indices(op, pn_ia32_fst_X_regular, pn_ia32_fst_X_except);
8234  set_op_tag(op, ia32_op_tag);
8235  ia32_init_op(op, 2);
8236  op_ia32_fst = op;
8237  op = new_ir_op(cur_opcode + iro_ia32_fstp, "ia32_fstp", op_pin_state_exc_pinned, irop_flag_fragile|irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_x87_attr_t));
8238  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
8239  set_op_attrs_equal(op, ia32_x87_attrs_equal);
8240  set_op_copy_attr(op, be_copy_attr);
8241  ir_op_set_memory_index(op, n_ia32_fstp_mem);
8242  ir_op_set_fragile_indices(op, pn_ia32_fstp_X_regular, pn_ia32_fstp_X_except);
8243  set_op_tag(op, ia32_op_tag);
8244  ia32_init_op(op, 2);
8245  op_ia32_fstp = op;
8246  op = new_ir_op(cur_opcode + iro_ia32_fsub, "ia32_fsub", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_x87_attr_t));
8247  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
8248  set_op_attrs_equal(op, ia32_x87_attrs_equal);
8249  set_op_copy_attr(op, be_copy_attr);
8250  set_op_tag(op, ia32_op_tag);
8251  ia32_init_op(op, 4);
8252  op_ia32_fsub = op;
8253  op = new_ir_op(cur_opcode + iro_ia32_fxch, "ia32_fxch", op_pin_state_floats, irop_flag_keep, oparity_any, -1, sizeof(ia32_x87_attr_t));
8254  set_op_dump(op, ia32_dump_node);
8255  set_op_attrs_equal(op, attrs_equal_false);
8256  set_op_copy_attr(op, be_copy_attr);
8257  set_op_tag(op, ia32_op_tag);
8258  ia32_init_op(op, 1);
8259  op_ia32_fxch = op;
8260  op = new_ir_op(cur_opcode + iro_ia32_l_Adc, "ia32_l_Adc", op_pin_state_floats, irop_flag_none, oparity_any, -1, 0);
8261  set_op_dump(op, NULL);
8262  set_op_tag(op, ia32_op_tag);
8263  ia32_init_op(op, 0);
8264  op_ia32_l_Adc = op;
8265  op = new_ir_op(cur_opcode + iro_ia32_l_Add, "ia32_l_Add", op_pin_state_floats, irop_flag_none, oparity_any, -1, 0);
8266  set_op_dump(op, NULL);
8267  set_op_tag(op, ia32_op_tag);
8268  ia32_init_op(op, 0);
8269  op_ia32_l_Add = op;
8270  op = new_ir_op(cur_opcode + iro_ia32_l_FloattoLL, "ia32_l_FloattoLL", op_pin_state_floats, irop_flag_none, oparity_any, -1, 0);
8271  set_op_dump(op, NULL);
8272  set_op_tag(op, ia32_op_tag);
8273  ia32_init_op(op, 0);
8274  op_ia32_l_FloattoLL = op;
8275  op = new_ir_op(cur_opcode + iro_ia32_l_IMul, "ia32_l_IMul", op_pin_state_floats, irop_flag_none, oparity_any, -1, 0);
8276  set_op_dump(op, NULL);
8277  set_op_tag(op, ia32_op_tag);
8278  ia32_init_op(op, 0);
8279  op_ia32_l_IMul = op;
8280  op = new_ir_op(cur_opcode + iro_ia32_l_LLtoFloat, "ia32_l_LLtoFloat", op_pin_state_floats, irop_flag_none, oparity_any, -1, 0);
8281  set_op_dump(op, NULL);
8282  set_op_tag(op, ia32_op_tag);
8283  ia32_init_op(op, 0);
8284  op_ia32_l_LLtoFloat = op;
8285  op = new_ir_op(cur_opcode + iro_ia32_l_Minus64, "ia32_l_Minus64", op_pin_state_floats, irop_flag_none, oparity_any, -1, 0);
8286  set_op_dump(op, NULL);
8287  set_op_tag(op, ia32_op_tag);
8288  ia32_init_op(op, 0);
8289  op_ia32_l_Minus64 = op;
8290  op = new_ir_op(cur_opcode + iro_ia32_l_Mul, "ia32_l_Mul", op_pin_state_floats, irop_flag_none, oparity_any, -1, 0);
8291  set_op_dump(op, NULL);
8292  set_op_tag(op, ia32_op_tag);
8293  ia32_init_op(op, 0);
8294  op_ia32_l_Mul = op;
8295  op = new_ir_op(cur_opcode + iro_ia32_l_Sbb, "ia32_l_Sbb", op_pin_state_floats, irop_flag_none, oparity_any, -1, 0);
8296  set_op_dump(op, NULL);
8297  set_op_tag(op, ia32_op_tag);
8298  ia32_init_op(op, 0);
8299  op_ia32_l_Sbb = op;
8300  op = new_ir_op(cur_opcode + iro_ia32_l_Sub, "ia32_l_Sub", op_pin_state_floats, irop_flag_none, oparity_any, -1, 0);
8301  set_op_dump(op, NULL);
8302  set_op_tag(op, ia32_op_tag);
8303  ia32_init_op(op, 0);
8304  op_ia32_l_Sub = op;
8305  op = new_ir_op(cur_opcode + iro_ia32_xAllOnes, "ia32_xAllOnes", op_pin_state_floats, irop_flag_constlike, oparity_any, -1, sizeof(ia32_attr_t));
8306  set_op_dump(op, ia32_dump_node);
8307  set_op_attrs_equal(op, ia32_attrs_equal);
8308  set_op_copy_attr(op, be_copy_attr);
8309  set_op_tag(op, ia32_op_tag);
8310  ia32_init_op(op, 3);
8311  op_ia32_xAllOnes = op;
8312  op = new_ir_op(cur_opcode + iro_ia32_xLoad, "ia32_xLoad", op_pin_state_exc_pinned, irop_flag_fragile|irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
8313  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
8314  set_op_attrs_equal(op, ia32_attrs_equal);
8315  set_op_copy_attr(op, be_copy_attr);
8316  ir_op_set_memory_index(op, n_ia32_xLoad_mem);
8317  ir_op_set_fragile_indices(op, pn_ia32_xLoad_X_regular, pn_ia32_xLoad_X_except);
8318  set_op_tag(op, ia32_op_tag);
8319  ia32_init_op(op, 0);
8320  op_ia32_xLoad = op;
8321  op = new_ir_op(cur_opcode + iro_ia32_xPzero, "ia32_xPzero", op_pin_state_floats, irop_flag_constlike, oparity_any, -1, sizeof(ia32_attr_t));
8322  set_op_dump(op, ia32_dump_node);
8323  set_op_attrs_equal(op, ia32_attrs_equal);
8324  set_op_copy_attr(op, be_copy_attr);
8325  set_op_tag(op, ia32_op_tag);
8326  ia32_init_op(op, 3);
8327  op_ia32_xPzero = op;
8328  op = new_ir_op(cur_opcode + iro_ia32_xStore, "ia32_xStore", op_pin_state_exc_pinned, irop_flag_fragile|irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
8329  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
8330  set_op_attrs_equal(op, ia32_attrs_equal);
8331  set_op_copy_attr(op, be_copy_attr);
8332  ir_op_set_memory_index(op, n_ia32_xStore_mem);
8333  ir_op_set_fragile_indices(op, pn_ia32_xStore_X_regular, pn_ia32_xStore_X_except);
8334  set_op_tag(op, ia32_op_tag);
8335  ia32_init_op(op, 0);
8336  op_ia32_xStore = op;
8337  op = new_ir_op(cur_opcode + iro_ia32_xZero, "ia32_xZero", op_pin_state_floats, irop_flag_constlike, oparity_any, -1, sizeof(ia32_attr_t));
8338  set_op_dump(op, ia32_dump_node);
8339  set_op_attrs_equal(op, ia32_attrs_equal);
8340  set_op_copy_attr(op, be_copy_attr);
8341  set_op_tag(op, ia32_op_tag);
8342  ia32_init_op(op, 3);
8343  op_ia32_xZero = op;
8344  op = new_ir_op(cur_opcode + iro_ia32_xxLoad, "ia32_xxLoad", op_pin_state_exc_pinned, irop_flag_fragile|irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
8345  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
8346  set_op_attrs_equal(op, ia32_attrs_equal);
8347  set_op_copy_attr(op, be_copy_attr);
8348  ir_op_set_memory_index(op, n_ia32_xxLoad_mem);
8349  ir_op_set_fragile_indices(op, pn_ia32_xxLoad_X_regular, pn_ia32_xxLoad_X_except);
8350  set_op_tag(op, ia32_op_tag);
8351  ia32_init_op(op, 1);
8352  op_ia32_xxLoad = op;
8353  op = new_ir_op(cur_opcode + iro_ia32_xxStore, "ia32_xxStore", op_pin_state_exc_pinned, irop_flag_fragile|irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
8354  ir_op_set_memory_index(op, 2); set_op_dump(op, ia32_dump_node);
8355  set_op_attrs_equal(op, ia32_attrs_equal);
8356  set_op_copy_attr(op, be_copy_attr);
8357  ir_op_set_memory_index(op, n_ia32_xxStore_mem);
8358  ir_op_set_fragile_indices(op, pn_ia32_xxStore_X_regular, pn_ia32_xxStore_X_except);
8359  set_op_tag(op, ia32_op_tag);
8360  ia32_init_op(op, 1);
8361  op_ia32_xxStore = op;
8362 
8363 }
8364 
8365 void ia32_free_opcodes(void)
8366 {
8367  free_ir_op(op_ia32_Adc); op_ia32_Adc = NULL;
8368  free_ir_op(op_ia32_Add); op_ia32_Add = NULL;
8369  free_ir_op(op_ia32_AddMem); op_ia32_AddMem = NULL;
8370  free_ir_op(op_ia32_AddSP); op_ia32_AddSP = NULL;
8371  free_ir_op(op_ia32_Adds); op_ia32_Adds = NULL;
8372  free_ir_op(op_ia32_And); op_ia32_And = NULL;
8373  free_ir_op(op_ia32_AndMem); op_ia32_AndMem = NULL;
8374  free_ir_op(op_ia32_Andnp); op_ia32_Andnp = NULL;
8375  free_ir_op(op_ia32_Andp); op_ia32_Andp = NULL;
8376  free_ir_op(op_ia32_Breakpoint); op_ia32_Breakpoint = NULL;
8377  free_ir_op(op_ia32_Bsf); op_ia32_Bsf = NULL;
8378  free_ir_op(op_ia32_Bsr); op_ia32_Bsr = NULL;
8379  free_ir_op(op_ia32_Bswap); op_ia32_Bswap = NULL;
8380  free_ir_op(op_ia32_Bswap16); op_ia32_Bswap16 = NULL;
8381  free_ir_op(op_ia32_Bt); op_ia32_Bt = NULL;
8382  free_ir_op(op_ia32_CMovcc); op_ia32_CMovcc = NULL;
8383  free_ir_op(op_ia32_Call); op_ia32_Call = NULL;
8384  free_ir_op(op_ia32_ChangeCW); op_ia32_ChangeCW = NULL;
8385  free_ir_op(op_ia32_Cltd); op_ia32_Cltd = NULL;
8386  free_ir_op(op_ia32_Cmc); op_ia32_Cmc = NULL;
8387  free_ir_op(op_ia32_Cmp); op_ia32_Cmp = NULL;
8388  free_ir_op(op_ia32_CmpXChgMem); op_ia32_CmpXChgMem = NULL;
8389  free_ir_op(op_ia32_Const); op_ia32_Const = NULL;
8390  free_ir_op(op_ia32_Conv_FP2FP); op_ia32_Conv_FP2FP = NULL;
8391  free_ir_op(op_ia32_Conv_FP2I); op_ia32_Conv_FP2I = NULL;
8392  free_ir_op(op_ia32_Conv_I2FP); op_ia32_Conv_I2FP = NULL;
8393  free_ir_op(op_ia32_Conv_I2I); op_ia32_Conv_I2I = NULL;
8394  free_ir_op(op_ia32_CopyB); op_ia32_CopyB = NULL;
8395  free_ir_op(op_ia32_CopyB_i); op_ia32_CopyB_i = NULL;
8396  free_ir_op(op_ia32_CopyEbpEsp); op_ia32_CopyEbpEsp = NULL;
8397  free_ir_op(op_ia32_CvtSI2SD); op_ia32_CvtSI2SD = NULL;
8398  free_ir_op(op_ia32_CvtSI2SS); op_ia32_CvtSI2SS = NULL;
8399  free_ir_op(op_ia32_Cwtl); op_ia32_Cwtl = NULL;
8400  free_ir_op(op_ia32_Dec); op_ia32_Dec = NULL;
8401  free_ir_op(op_ia32_DecMem); op_ia32_DecMem = NULL;
8402  free_ir_op(op_ia32_Div); op_ia32_Div = NULL;
8403  free_ir_op(op_ia32_Divs); op_ia32_Divs = NULL;
8404  free_ir_op(op_ia32_Enter); op_ia32_Enter = NULL;
8405  free_ir_op(op_ia32_FldCW); op_ia32_FldCW = NULL;
8406  free_ir_op(op_ia32_FnstCW); op_ia32_FnstCW = NULL;
8407  free_ir_op(op_ia32_FnstCWNOP); op_ia32_FnstCWNOP = NULL;
8408  free_ir_op(op_ia32_FtstFnstsw); op_ia32_FtstFnstsw = NULL;
8409  free_ir_op(op_ia32_FucomFnstsw); op_ia32_FucomFnstsw = NULL;
8410  free_ir_op(op_ia32_Fucomi); op_ia32_Fucomi = NULL;
8411  free_ir_op(op_ia32_FucomppFnstsw); op_ia32_FucomppFnstsw = NULL;
8412  free_ir_op(op_ia32_GetEIP); op_ia32_GetEIP = NULL;
8413  free_ir_op(op_ia32_IDiv); op_ia32_IDiv = NULL;
8414  free_ir_op(op_ia32_IJmp); op_ia32_IJmp = NULL;
8415  free_ir_op(op_ia32_IMul); op_ia32_IMul = NULL;
8416  free_ir_op(op_ia32_IMul1OP); op_ia32_IMul1OP = NULL;
8417  free_ir_op(op_ia32_IMulImm); op_ia32_IMulImm = NULL;
8418  free_ir_op(op_ia32_Immediate); op_ia32_Immediate = NULL;
8419  free_ir_op(op_ia32_Inc); op_ia32_Inc = NULL;
8420  free_ir_op(op_ia32_IncMem); op_ia32_IncMem = NULL;
8421  free_ir_op(op_ia32_Inport); op_ia32_Inport = NULL;
8422  free_ir_op(op_ia32_Jcc); op_ia32_Jcc = NULL;
8423  free_ir_op(op_ia32_Jmp); op_ia32_Jmp = NULL;
8424  free_ir_op(op_ia32_LdTls); op_ia32_LdTls = NULL;
8425  free_ir_op(op_ia32_Lea); op_ia32_Lea = NULL;
8426  free_ir_op(op_ia32_Leave); op_ia32_Leave = NULL;
8427  free_ir_op(op_ia32_Load); op_ia32_Load = NULL;
8428  free_ir_op(op_ia32_Maxs); op_ia32_Maxs = NULL;
8429  free_ir_op(op_ia32_Mins); op_ia32_Mins = NULL;
8430  free_ir_op(op_ia32_Minus64); op_ia32_Minus64 = NULL;
8431  free_ir_op(op_ia32_Movd); op_ia32_Movd = NULL;
8432  free_ir_op(op_ia32_Mul); op_ia32_Mul = NULL;
8433  free_ir_op(op_ia32_Muls); op_ia32_Muls = NULL;
8434  free_ir_op(op_ia32_Neg); op_ia32_Neg = NULL;
8435  free_ir_op(op_ia32_NegMem); op_ia32_NegMem = NULL;
8436  free_ir_op(op_ia32_NoReg_FP); op_ia32_NoReg_FP = NULL;
8437  free_ir_op(op_ia32_NoReg_GP); op_ia32_NoReg_GP = NULL;
8438  free_ir_op(op_ia32_NoReg_XMM); op_ia32_NoReg_XMM = NULL;
8439  free_ir_op(op_ia32_Not); op_ia32_Not = NULL;
8440  free_ir_op(op_ia32_NotMem); op_ia32_NotMem = NULL;
8441  free_ir_op(op_ia32_Or); op_ia32_Or = NULL;
8442  free_ir_op(op_ia32_OrMem); op_ia32_OrMem = NULL;
8443  free_ir_op(op_ia32_Orp); op_ia32_Orp = NULL;
8444  free_ir_op(op_ia32_Outport); op_ia32_Outport = NULL;
8445  free_ir_op(op_ia32_Pop); op_ia32_Pop = NULL;
8446  free_ir_op(op_ia32_PopMem); op_ia32_PopMem = NULL;
8447  free_ir_op(op_ia32_Popcnt); op_ia32_Popcnt = NULL;
8448  free_ir_op(op_ia32_Prefetch); op_ia32_Prefetch = NULL;
8449  free_ir_op(op_ia32_PrefetchNTA); op_ia32_PrefetchNTA = NULL;
8450  free_ir_op(op_ia32_PrefetchT0); op_ia32_PrefetchT0 = NULL;
8451  free_ir_op(op_ia32_PrefetchT1); op_ia32_PrefetchT1 = NULL;
8452  free_ir_op(op_ia32_PrefetchT2); op_ia32_PrefetchT2 = NULL;
8453  free_ir_op(op_ia32_PrefetchW); op_ia32_PrefetchW = NULL;
8454  free_ir_op(op_ia32_Pslld); op_ia32_Pslld = NULL;
8455  free_ir_op(op_ia32_Psllq); op_ia32_Psllq = NULL;
8456  free_ir_op(op_ia32_Psrld); op_ia32_Psrld = NULL;
8457  free_ir_op(op_ia32_Push); op_ia32_Push = NULL;
8458  free_ir_op(op_ia32_PushEax); op_ia32_PushEax = NULL;
8459  free_ir_op(op_ia32_Ret); op_ia32_Ret = NULL;
8460  free_ir_op(op_ia32_Rol); op_ia32_Rol = NULL;
8461  free_ir_op(op_ia32_RolMem); op_ia32_RolMem = NULL;
8462  free_ir_op(op_ia32_Ror); op_ia32_Ror = NULL;
8463  free_ir_op(op_ia32_RorMem); op_ia32_RorMem = NULL;
8464  free_ir_op(op_ia32_Sahf); op_ia32_Sahf = NULL;
8465  free_ir_op(op_ia32_Sar); op_ia32_Sar = NULL;
8466  free_ir_op(op_ia32_SarMem); op_ia32_SarMem = NULL;
8467  free_ir_op(op_ia32_Sbb); op_ia32_Sbb = NULL;
8468  free_ir_op(op_ia32_Sbb0); op_ia32_Sbb0 = NULL;
8469  free_ir_op(op_ia32_Setcc); op_ia32_Setcc = NULL;
8470  free_ir_op(op_ia32_SetccMem); op_ia32_SetccMem = NULL;
8471  free_ir_op(op_ia32_Shl); op_ia32_Shl = NULL;
8472  free_ir_op(op_ia32_ShlD); op_ia32_ShlD = NULL;
8473  free_ir_op(op_ia32_ShlMem); op_ia32_ShlMem = NULL;
8474  free_ir_op(op_ia32_Shr); op_ia32_Shr = NULL;
8475  free_ir_op(op_ia32_ShrD); op_ia32_ShrD = NULL;
8476  free_ir_op(op_ia32_ShrMem); op_ia32_ShrMem = NULL;
8477  free_ir_op(op_ia32_Stc); op_ia32_Stc = NULL;
8478  free_ir_op(op_ia32_Store); op_ia32_Store = NULL;
8479  free_ir_op(op_ia32_Sub); op_ia32_Sub = NULL;
8480  free_ir_op(op_ia32_SubMem); op_ia32_SubMem = NULL;
8481  free_ir_op(op_ia32_SubSP); op_ia32_SubSP = NULL;
8482  free_ir_op(op_ia32_Subs); op_ia32_Subs = NULL;
8483  free_ir_op(op_ia32_SwitchJmp); op_ia32_SwitchJmp = NULL;
8484  free_ir_op(op_ia32_Test); op_ia32_Test = NULL;
8485  free_ir_op(op_ia32_UD2); op_ia32_UD2 = NULL;
8486  free_ir_op(op_ia32_Ucomis); op_ia32_Ucomis = NULL;
8487  free_ir_op(op_ia32_Xor); op_ia32_Xor = NULL;
8488  free_ir_op(op_ia32_Xor0); op_ia32_Xor0 = NULL;
8489  free_ir_op(op_ia32_XorHighLow); op_ia32_XorHighLow = NULL;
8490  free_ir_op(op_ia32_XorMem); op_ia32_XorMem = NULL;
8491  free_ir_op(op_ia32_Xorp); op_ia32_Xorp = NULL;
8492  free_ir_op(op_ia32_emms); op_ia32_emms = NULL;
8493  free_ir_op(op_ia32_fabs); op_ia32_fabs = NULL;
8494  free_ir_op(op_ia32_fadd); op_ia32_fadd = NULL;
8495  free_ir_op(op_ia32_fchs); op_ia32_fchs = NULL;
8496  free_ir_op(op_ia32_fdiv); op_ia32_fdiv = NULL;
8497  free_ir_op(op_ia32_fdup); op_ia32_fdup = NULL;
8498  free_ir_op(op_ia32_femms); op_ia32_femms = NULL;
8499  free_ir_op(op_ia32_ffreep); op_ia32_ffreep = NULL;
8500  free_ir_op(op_ia32_fild); op_ia32_fild = NULL;
8501  free_ir_op(op_ia32_fist); op_ia32_fist = NULL;
8502  free_ir_op(op_ia32_fistp); op_ia32_fistp = NULL;
8503  free_ir_op(op_ia32_fisttp); op_ia32_fisttp = NULL;
8504  free_ir_op(op_ia32_fld); op_ia32_fld = NULL;
8505  free_ir_op(op_ia32_fld1); op_ia32_fld1 = NULL;
8506  free_ir_op(op_ia32_fldl2e); op_ia32_fldl2e = NULL;
8507  free_ir_op(op_ia32_fldl2t); op_ia32_fldl2t = NULL;
8508  free_ir_op(op_ia32_fldlg2); op_ia32_fldlg2 = NULL;
8509  free_ir_op(op_ia32_fldln2); op_ia32_fldln2 = NULL;
8510  free_ir_op(op_ia32_fldpi); op_ia32_fldpi = NULL;
8511  free_ir_op(op_ia32_fldz); op_ia32_fldz = NULL;
8512  free_ir_op(op_ia32_fmul); op_ia32_fmul = NULL;
8513  free_ir_op(op_ia32_fpop); op_ia32_fpop = NULL;
8514  free_ir_op(op_ia32_fst); op_ia32_fst = NULL;
8515  free_ir_op(op_ia32_fstp); op_ia32_fstp = NULL;
8516  free_ir_op(op_ia32_fsub); op_ia32_fsub = NULL;
8517  free_ir_op(op_ia32_fxch); op_ia32_fxch = NULL;
8518  free_ir_op(op_ia32_l_Adc); op_ia32_l_Adc = NULL;
8519  free_ir_op(op_ia32_l_Add); op_ia32_l_Add = NULL;
8520  free_ir_op(op_ia32_l_FloattoLL); op_ia32_l_FloattoLL = NULL;
8521  free_ir_op(op_ia32_l_IMul); op_ia32_l_IMul = NULL;
8522  free_ir_op(op_ia32_l_LLtoFloat); op_ia32_l_LLtoFloat = NULL;
8523  free_ir_op(op_ia32_l_Minus64); op_ia32_l_Minus64 = NULL;
8524  free_ir_op(op_ia32_l_Mul); op_ia32_l_Mul = NULL;
8525  free_ir_op(op_ia32_l_Sbb); op_ia32_l_Sbb = NULL;
8526  free_ir_op(op_ia32_l_Sub); op_ia32_l_Sub = NULL;
8527  free_ir_op(op_ia32_xAllOnes); op_ia32_xAllOnes = NULL;
8528  free_ir_op(op_ia32_xLoad); op_ia32_xLoad = NULL;
8529  free_ir_op(op_ia32_xPzero); op_ia32_xPzero = NULL;
8530  free_ir_op(op_ia32_xStore); op_ia32_xStore = NULL;
8531  free_ir_op(op_ia32_xZero); op_ia32_xZero = NULL;
8532  free_ir_op(op_ia32_xxLoad); op_ia32_xxLoad = NULL;
8533  free_ir_op(op_ia32_xxStore); op_ia32_xxStore = NULL;
8534 
8535 }
set_op_dump
void set_op_dump(ir_op *op, dump_node_func func)
Sets dump callback func for operation op.
irop_flag_fragile
Set if the operation can change the control flow because of an exception.
Definition: irop.h:45
irop_flag_dump_noblock
node should be dumped outside any blocks
Definition: irop.h:54
ir_op_set_fragile_indices
void ir_op_set_fragile_indices(ir_op *op, unsigned pn_x_regular, unsigned pn_x_except)
Sets proj-number for X_regular and X_except projs of fragile nodes.
get_irn_generic_attr
void * get_irn_generic_attr(ir_node *node)
Returns a pointer to the node attributes.
mode_X
ir_mode * mode_X
execution
Definition: irmode.h:205
get_next_ir_opcodes
unsigned get_next_ir_opcodes(unsigned num)
Returns the next free n IR opcode number, allows to register a bunch of user ops. ...
set_op_attrs_equal
void set_op_attrs_equal(ir_op *op, node_attrs_equal_func func)
Sets attrs_equal callback func for operation op.
new_ir_op
ir_op * new_ir_op(unsigned code, const char *name, op_pin_state p, irop_flags flags, op_arity opar, int op_index, size_t attr_size)
Creates a new IR operation.
op_pin_state_floats
Nodes of this opcode can be placed in any basic block.
Definition: firm_types.h:202
ir_graph
struct ir_graph ir_graph
Procedure Graph.
Definition: firm_types.h:74
mode_ANY
ir_mode * mode_ANY
undefined mode
Definition: irmode.h:209
dbg_info
struct dbg_info dbg_info
Source Reference.
Definition: firm_types.h:40
ir_node
struct ir_node ir_node
Procedure Graph Node.
Definition: firm_types.h:53
irop_flag_forking
Forking control flow at this operation.
Definition: irop.h:48
ir_mode
struct ir_mode ir_mode
SSA Value mode.
Definition: firm_types.h:59
new_ir_node
ir_node * new_ir_node(dbg_info *db, ir_graph *irg, ir_node *block, ir_op *op, ir_mode *mode, int arity, ir_node *const *in)
IR node constructor.
irop_flag_cfopcode
This operation is a control flow operation.
Definition: irop.h:44
get_irn_opcode
unsigned get_irn_opcode(const ir_node *node)
Returns the opcode-enum of the node.
ir_switch_table
struct ir_switch_table ir_switch_table
A switch table mapping integer numbers to proj-numbers of a Switch-node.
Definition: firm_types.h:105
irop_flag_keep
This operation can be kept in End's keep-alive list.
Definition: irop.h:51
ir_entity
struct ir_entity ir_entity
Entity.
Definition: firm_types.h:83
get_irn_irg
ir_graph * get_irn_irg(const ir_node *node)
Returns the ir_graph this node belongs to.
mode_M
ir_mode * mode_M
memory
Definition: irmode.h:178
op_pin_state_exc_pinned
Node must remain in this basic block if it can throw an exception, else can float.
Definition: firm_types.h:204
get_irn_op
ir_op * get_irn_op(const ir_node *node)
Returns the opcode struct of the node.
ir_op_set_memory_index
void ir_op_set_memory_index(ir_op *op, int memory_index)
Sets memory input of operation using memory.
ir_op
struct ir_op ir_op
Node Opcode.
Definition: firm_types.h:56
optimize_node
ir_node * optimize_node(ir_node *n)
Applies local optimizations to a single node.
free_ir_op
void free_ir_op(ir_op *code)
Frees an ir operation.
op_pin_state_pinned
Nodes must remain in this basic block.
Definition: firm_types.h:203
irop_flag_unknown_jump
This operation jumps to an unknown destination.
Definition: irop.h:58
mode_T
ir_mode * mode_T
tuple (none)
Definition: irmode.h:208
irop_flag_none
Nothing.
Definition: irop.h:42
irop_flag_constlike
This operation has no arguments and is some kind of a constant.
Definition: irop.h:49
set_op_hash
void set_op_hash(ir_op *op, hash_func func)
Sets hash callback func for operation op.
verify_new_node
void verify_new_node(ir_node *node)
If firm is built in debug mode, verify that a newly created node is fine.
set_op_copy_attr
void set_op_copy_attr(ir_op *op, copy_attr_func func)
Sets attribute copy callback func for operation op.
irop_flag_uses_memory
This operation has a memory input and may change the memory state.
Definition: irop.h:53
oparity_any
Any other arity, either fixed for the opcode or known when creating the node.
Definition: irop.h:36