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gen_mips_regalloc_if.c
1 
11 #include "gen_mips_regalloc_if.h"
12 
13 #include "mips_bearch_t.h"
14 
15 const arch_register_req_t mips_class_reg_req_gp = {
16  .cls = &mips_reg_classes[CLASS_mips_gp],
17  .width = 1,
18 };
19 static const unsigned mips_limited_gp_zero[] = { (1U << REG_GP_ZERO) };
20 const arch_register_req_t mips_single_reg_req_gp_zero = {
21  .cls = &mips_reg_classes[CLASS_mips_gp],
22  .limited = mips_limited_gp_zero,
23  .width = 1,
24 };
25 static const unsigned mips_limited_gp_at[] = { (1U << REG_GP_AT) };
26 const arch_register_req_t mips_single_reg_req_gp_at = {
27  .cls = &mips_reg_classes[CLASS_mips_gp],
28  .limited = mips_limited_gp_at,
29  .width = 1,
30 };
31 static const unsigned mips_limited_gp_v0[] = { (1U << REG_GP_V0) };
32 const arch_register_req_t mips_single_reg_req_gp_v0 = {
33  .cls = &mips_reg_classes[CLASS_mips_gp],
34  .limited = mips_limited_gp_v0,
35  .width = 1,
36 };
37 static const unsigned mips_limited_gp_v1[] = { (1U << REG_GP_V1) };
38 const arch_register_req_t mips_single_reg_req_gp_v1 = {
39  .cls = &mips_reg_classes[CLASS_mips_gp],
40  .limited = mips_limited_gp_v1,
41  .width = 1,
42 };
43 static const unsigned mips_limited_gp_a0[] = { (1U << REG_GP_A0) };
44 const arch_register_req_t mips_single_reg_req_gp_a0 = {
45  .cls = &mips_reg_classes[CLASS_mips_gp],
46  .limited = mips_limited_gp_a0,
47  .width = 1,
48 };
49 static const unsigned mips_limited_gp_a1[] = { (1U << REG_GP_A1) };
50 const arch_register_req_t mips_single_reg_req_gp_a1 = {
51  .cls = &mips_reg_classes[CLASS_mips_gp],
52  .limited = mips_limited_gp_a1,
53  .width = 1,
54 };
55 static const unsigned mips_limited_gp_a2[] = { (1U << REG_GP_A2) };
56 const arch_register_req_t mips_single_reg_req_gp_a2 = {
57  .cls = &mips_reg_classes[CLASS_mips_gp],
58  .limited = mips_limited_gp_a2,
59  .width = 1,
60 };
61 static const unsigned mips_limited_gp_a3[] = { (1U << REG_GP_A3) };
62 const arch_register_req_t mips_single_reg_req_gp_a3 = {
63  .cls = &mips_reg_classes[CLASS_mips_gp],
64  .limited = mips_limited_gp_a3,
65  .width = 1,
66 };
67 static const unsigned mips_limited_gp_t0[] = { (1U << REG_GP_T0) };
68 const arch_register_req_t mips_single_reg_req_gp_t0 = {
69  .cls = &mips_reg_classes[CLASS_mips_gp],
70  .limited = mips_limited_gp_t0,
71  .width = 1,
72 };
73 static const unsigned mips_limited_gp_t1[] = { (1U << REG_GP_T1) };
74 const arch_register_req_t mips_single_reg_req_gp_t1 = {
75  .cls = &mips_reg_classes[CLASS_mips_gp],
76  .limited = mips_limited_gp_t1,
77  .width = 1,
78 };
79 static const unsigned mips_limited_gp_t2[] = { (1U << REG_GP_T2) };
80 const arch_register_req_t mips_single_reg_req_gp_t2 = {
81  .cls = &mips_reg_classes[CLASS_mips_gp],
82  .limited = mips_limited_gp_t2,
83  .width = 1,
84 };
85 static const unsigned mips_limited_gp_t3[] = { (1U << REG_GP_T3) };
86 const arch_register_req_t mips_single_reg_req_gp_t3 = {
87  .cls = &mips_reg_classes[CLASS_mips_gp],
88  .limited = mips_limited_gp_t3,
89  .width = 1,
90 };
91 static const unsigned mips_limited_gp_t4[] = { (1U << REG_GP_T4) };
92 const arch_register_req_t mips_single_reg_req_gp_t4 = {
93  .cls = &mips_reg_classes[CLASS_mips_gp],
94  .limited = mips_limited_gp_t4,
95  .width = 1,
96 };
97 static const unsigned mips_limited_gp_t5[] = { (1U << REG_GP_T5) };
98 const arch_register_req_t mips_single_reg_req_gp_t5 = {
99  .cls = &mips_reg_classes[CLASS_mips_gp],
100  .limited = mips_limited_gp_t5,
101  .width = 1,
102 };
103 static const unsigned mips_limited_gp_t6[] = { (1U << REG_GP_T6) };
104 const arch_register_req_t mips_single_reg_req_gp_t6 = {
105  .cls = &mips_reg_classes[CLASS_mips_gp],
106  .limited = mips_limited_gp_t6,
107  .width = 1,
108 };
109 static const unsigned mips_limited_gp_t7[] = { (1U << REG_GP_T7) };
110 const arch_register_req_t mips_single_reg_req_gp_t7 = {
111  .cls = &mips_reg_classes[CLASS_mips_gp],
112  .limited = mips_limited_gp_t7,
113  .width = 1,
114 };
115 static const unsigned mips_limited_gp_s0[] = { (1U << REG_GP_S0) };
116 const arch_register_req_t mips_single_reg_req_gp_s0 = {
117  .cls = &mips_reg_classes[CLASS_mips_gp],
118  .limited = mips_limited_gp_s0,
119  .width = 1,
120 };
121 static const unsigned mips_limited_gp_s1[] = { (1U << REG_GP_S1) };
122 const arch_register_req_t mips_single_reg_req_gp_s1 = {
123  .cls = &mips_reg_classes[CLASS_mips_gp],
124  .limited = mips_limited_gp_s1,
125  .width = 1,
126 };
127 static const unsigned mips_limited_gp_s2[] = { (1U << REG_GP_S2) };
128 const arch_register_req_t mips_single_reg_req_gp_s2 = {
129  .cls = &mips_reg_classes[CLASS_mips_gp],
130  .limited = mips_limited_gp_s2,
131  .width = 1,
132 };
133 static const unsigned mips_limited_gp_s3[] = { (1U << REG_GP_S3) };
134 const arch_register_req_t mips_single_reg_req_gp_s3 = {
135  .cls = &mips_reg_classes[CLASS_mips_gp],
136  .limited = mips_limited_gp_s3,
137  .width = 1,
138 };
139 static const unsigned mips_limited_gp_s4[] = { (1U << REG_GP_S4) };
140 const arch_register_req_t mips_single_reg_req_gp_s4 = {
141  .cls = &mips_reg_classes[CLASS_mips_gp],
142  .limited = mips_limited_gp_s4,
143  .width = 1,
144 };
145 static const unsigned mips_limited_gp_s5[] = { (1U << REG_GP_S5) };
146 const arch_register_req_t mips_single_reg_req_gp_s5 = {
147  .cls = &mips_reg_classes[CLASS_mips_gp],
148  .limited = mips_limited_gp_s5,
149  .width = 1,
150 };
151 static const unsigned mips_limited_gp_s6[] = { (1U << REG_GP_S6) };
152 const arch_register_req_t mips_single_reg_req_gp_s6 = {
153  .cls = &mips_reg_classes[CLASS_mips_gp],
154  .limited = mips_limited_gp_s6,
155  .width = 1,
156 };
157 static const unsigned mips_limited_gp_s7[] = { (1U << REG_GP_S7) };
158 const arch_register_req_t mips_single_reg_req_gp_s7 = {
159  .cls = &mips_reg_classes[CLASS_mips_gp],
160  .limited = mips_limited_gp_s7,
161  .width = 1,
162 };
163 static const unsigned mips_limited_gp_t8[] = { (1U << REG_GP_T8) };
164 const arch_register_req_t mips_single_reg_req_gp_t8 = {
165  .cls = &mips_reg_classes[CLASS_mips_gp],
166  .limited = mips_limited_gp_t8,
167  .width = 1,
168 };
169 static const unsigned mips_limited_gp_t9[] = { (1U << REG_GP_T9) };
170 const arch_register_req_t mips_single_reg_req_gp_t9 = {
171  .cls = &mips_reg_classes[CLASS_mips_gp],
172  .limited = mips_limited_gp_t9,
173  .width = 1,
174 };
175 static const unsigned mips_limited_gp_k0[] = { (1U << REG_GP_K0) };
176 const arch_register_req_t mips_single_reg_req_gp_k0 = {
177  .cls = &mips_reg_classes[CLASS_mips_gp],
178  .limited = mips_limited_gp_k0,
179  .width = 1,
180 };
181 static const unsigned mips_limited_gp_k1[] = { (1U << REG_GP_K1) };
182 const arch_register_req_t mips_single_reg_req_gp_k1 = {
183  .cls = &mips_reg_classes[CLASS_mips_gp],
184  .limited = mips_limited_gp_k1,
185  .width = 1,
186 };
187 static const unsigned mips_limited_gp_gp[] = { (1U << REG_GP_GP) };
188 const arch_register_req_t mips_single_reg_req_gp_gp = {
189  .cls = &mips_reg_classes[CLASS_mips_gp],
190  .limited = mips_limited_gp_gp,
191  .width = 1,
192 };
193 static const unsigned mips_limited_gp_sp[] = { (1U << REG_GP_SP) };
194 const arch_register_req_t mips_single_reg_req_gp_sp = {
195  .cls = &mips_reg_classes[CLASS_mips_gp],
196  .limited = mips_limited_gp_sp,
197  .width = 1,
198 };
199 static const unsigned mips_limited_gp_s8[] = { (1U << REG_GP_S8) };
200 const arch_register_req_t mips_single_reg_req_gp_s8 = {
201  .cls = &mips_reg_classes[CLASS_mips_gp],
202  .limited = mips_limited_gp_s8,
203  .width = 1,
204 };
205 static const unsigned mips_limited_gp_ra[] = { (1U << REG_GP_RA) };
206 const arch_register_req_t mips_single_reg_req_gp_ra = {
207  .cls = &mips_reg_classes[CLASS_mips_gp],
208  .limited = mips_limited_gp_ra,
209  .width = 1,
210 };
211 
212 
213 arch_register_class_t mips_reg_classes[] = {
214  {
215  .name = "mips_gp",
216  .mode = NULL,
217  .regs = &mips_registers[REG_ZERO],
218  .class_req = &mips_class_reg_req_gp,
219  .index = CLASS_mips_gp,
220  .n_regs = 32,
221  },
222 
223 };
224 
226 const arch_register_t mips_registers[] = {
227  {
228  .name = "zero",
229  .cls = &mips_reg_classes[CLASS_mips_gp],
230  .single_req = &mips_single_reg_req_gp_zero,
231  .index = REG_GP_ZERO,
232  .global_index = REG_ZERO,
233  .dwarf_number = 0,
234  .encoding = 0,
235  .is_virtual = false,
236  },
237  {
238  .name = "at",
239  .cls = &mips_reg_classes[CLASS_mips_gp],
240  .single_req = &mips_single_reg_req_gp_at,
241  .index = REG_GP_AT,
242  .global_index = REG_AT,
243  .dwarf_number = 0,
244  .encoding = 1,
245  .is_virtual = false,
246  },
247  {
248  .name = "v0",
249  .cls = &mips_reg_classes[CLASS_mips_gp],
250  .single_req = &mips_single_reg_req_gp_v0,
251  .index = REG_GP_V0,
252  .global_index = REG_V0,
253  .dwarf_number = 0,
254  .encoding = 2,
255  .is_virtual = false,
256  },
257  {
258  .name = "v1",
259  .cls = &mips_reg_classes[CLASS_mips_gp],
260  .single_req = &mips_single_reg_req_gp_v1,
261  .index = REG_GP_V1,
262  .global_index = REG_V1,
263  .dwarf_number = 0,
264  .encoding = 3,
265  .is_virtual = false,
266  },
267  {
268  .name = "a0",
269  .cls = &mips_reg_classes[CLASS_mips_gp],
270  .single_req = &mips_single_reg_req_gp_a0,
271  .index = REG_GP_A0,
272  .global_index = REG_A0,
273  .dwarf_number = 0,
274  .encoding = 4,
275  .is_virtual = false,
276  },
277  {
278  .name = "a1",
279  .cls = &mips_reg_classes[CLASS_mips_gp],
280  .single_req = &mips_single_reg_req_gp_a1,
281  .index = REG_GP_A1,
282  .global_index = REG_A1,
283  .dwarf_number = 0,
284  .encoding = 5,
285  .is_virtual = false,
286  },
287  {
288  .name = "a2",
289  .cls = &mips_reg_classes[CLASS_mips_gp],
290  .single_req = &mips_single_reg_req_gp_a2,
291  .index = REG_GP_A2,
292  .global_index = REG_A2,
293  .dwarf_number = 0,
294  .encoding = 6,
295  .is_virtual = false,
296  },
297  {
298  .name = "a3",
299  .cls = &mips_reg_classes[CLASS_mips_gp],
300  .single_req = &mips_single_reg_req_gp_a3,
301  .index = REG_GP_A3,
302  .global_index = REG_A3,
303  .dwarf_number = 0,
304  .encoding = 7,
305  .is_virtual = false,
306  },
307  {
308  .name = "t0",
309  .cls = &mips_reg_classes[CLASS_mips_gp],
310  .single_req = &mips_single_reg_req_gp_t0,
311  .index = REG_GP_T0,
312  .global_index = REG_T0,
313  .dwarf_number = 0,
314  .encoding = 8,
315  .is_virtual = false,
316  },
317  {
318  .name = "t1",
319  .cls = &mips_reg_classes[CLASS_mips_gp],
320  .single_req = &mips_single_reg_req_gp_t1,
321  .index = REG_GP_T1,
322  .global_index = REG_T1,
323  .dwarf_number = 0,
324  .encoding = 9,
325  .is_virtual = false,
326  },
327  {
328  .name = "t2",
329  .cls = &mips_reg_classes[CLASS_mips_gp],
330  .single_req = &mips_single_reg_req_gp_t2,
331  .index = REG_GP_T2,
332  .global_index = REG_T2,
333  .dwarf_number = 0,
334  .encoding = 10,
335  .is_virtual = false,
336  },
337  {
338  .name = "t3",
339  .cls = &mips_reg_classes[CLASS_mips_gp],
340  .single_req = &mips_single_reg_req_gp_t3,
341  .index = REG_GP_T3,
342  .global_index = REG_T3,
343  .dwarf_number = 0,
344  .encoding = 11,
345  .is_virtual = false,
346  },
347  {
348  .name = "t4",
349  .cls = &mips_reg_classes[CLASS_mips_gp],
350  .single_req = &mips_single_reg_req_gp_t4,
351  .index = REG_GP_T4,
352  .global_index = REG_T4,
353  .dwarf_number = 0,
354  .encoding = 12,
355  .is_virtual = false,
356  },
357  {
358  .name = "t5",
359  .cls = &mips_reg_classes[CLASS_mips_gp],
360  .single_req = &mips_single_reg_req_gp_t5,
361  .index = REG_GP_T5,
362  .global_index = REG_T5,
363  .dwarf_number = 0,
364  .encoding = 13,
365  .is_virtual = false,
366  },
367  {
368  .name = "t6",
369  .cls = &mips_reg_classes[CLASS_mips_gp],
370  .single_req = &mips_single_reg_req_gp_t6,
371  .index = REG_GP_T6,
372  .global_index = REG_T6,
373  .dwarf_number = 0,
374  .encoding = 14,
375  .is_virtual = false,
376  },
377  {
378  .name = "t7",
379  .cls = &mips_reg_classes[CLASS_mips_gp],
380  .single_req = &mips_single_reg_req_gp_t7,
381  .index = REG_GP_T7,
382  .global_index = REG_T7,
383  .dwarf_number = 0,
384  .encoding = 15,
385  .is_virtual = false,
386  },
387  {
388  .name = "s0",
389  .cls = &mips_reg_classes[CLASS_mips_gp],
390  .single_req = &mips_single_reg_req_gp_s0,
391  .index = REG_GP_S0,
392  .global_index = REG_S0,
393  .dwarf_number = 0,
394  .encoding = 16,
395  .is_virtual = false,
396  },
397  {
398  .name = "s1",
399  .cls = &mips_reg_classes[CLASS_mips_gp],
400  .single_req = &mips_single_reg_req_gp_s1,
401  .index = REG_GP_S1,
402  .global_index = REG_S1,
403  .dwarf_number = 0,
404  .encoding = 17,
405  .is_virtual = false,
406  },
407  {
408  .name = "s2",
409  .cls = &mips_reg_classes[CLASS_mips_gp],
410  .single_req = &mips_single_reg_req_gp_s2,
411  .index = REG_GP_S2,
412  .global_index = REG_S2,
413  .dwarf_number = 0,
414  .encoding = 18,
415  .is_virtual = false,
416  },
417  {
418  .name = "s3",
419  .cls = &mips_reg_classes[CLASS_mips_gp],
420  .single_req = &mips_single_reg_req_gp_s3,
421  .index = REG_GP_S3,
422  .global_index = REG_S3,
423  .dwarf_number = 0,
424  .encoding = 19,
425  .is_virtual = false,
426  },
427  {
428  .name = "s4",
429  .cls = &mips_reg_classes[CLASS_mips_gp],
430  .single_req = &mips_single_reg_req_gp_s4,
431  .index = REG_GP_S4,
432  .global_index = REG_S4,
433  .dwarf_number = 0,
434  .encoding = 20,
435  .is_virtual = false,
436  },
437  {
438  .name = "s5",
439  .cls = &mips_reg_classes[CLASS_mips_gp],
440  .single_req = &mips_single_reg_req_gp_s5,
441  .index = REG_GP_S5,
442  .global_index = REG_S5,
443  .dwarf_number = 0,
444  .encoding = 21,
445  .is_virtual = false,
446  },
447  {
448  .name = "s6",
449  .cls = &mips_reg_classes[CLASS_mips_gp],
450  .single_req = &mips_single_reg_req_gp_s6,
451  .index = REG_GP_S6,
452  .global_index = REG_S6,
453  .dwarf_number = 0,
454  .encoding = 22,
455  .is_virtual = false,
456  },
457  {
458  .name = "s7",
459  .cls = &mips_reg_classes[CLASS_mips_gp],
460  .single_req = &mips_single_reg_req_gp_s7,
461  .index = REG_GP_S7,
462  .global_index = REG_S7,
463  .dwarf_number = 0,
464  .encoding = 23,
465  .is_virtual = false,
466  },
467  {
468  .name = "t8",
469  .cls = &mips_reg_classes[CLASS_mips_gp],
470  .single_req = &mips_single_reg_req_gp_t8,
471  .index = REG_GP_T8,
472  .global_index = REG_T8,
473  .dwarf_number = 0,
474  .encoding = 24,
475  .is_virtual = false,
476  },
477  {
478  .name = "t9",
479  .cls = &mips_reg_classes[CLASS_mips_gp],
480  .single_req = &mips_single_reg_req_gp_t9,
481  .index = REG_GP_T9,
482  .global_index = REG_T9,
483  .dwarf_number = 0,
484  .encoding = 25,
485  .is_virtual = false,
486  },
487  {
488  .name = "k0",
489  .cls = &mips_reg_classes[CLASS_mips_gp],
490  .single_req = &mips_single_reg_req_gp_k0,
491  .index = REG_GP_K0,
492  .global_index = REG_K0,
493  .dwarf_number = 0,
494  .encoding = 26,
495  .is_virtual = false,
496  },
497  {
498  .name = "k1",
499  .cls = &mips_reg_classes[CLASS_mips_gp],
500  .single_req = &mips_single_reg_req_gp_k1,
501  .index = REG_GP_K1,
502  .global_index = REG_K1,
503  .dwarf_number = 0,
504  .encoding = 27,
505  .is_virtual = false,
506  },
507  {
508  .name = "gp",
509  .cls = &mips_reg_classes[CLASS_mips_gp],
510  .single_req = &mips_single_reg_req_gp_gp,
511  .index = REG_GP_GP,
512  .global_index = REG_GP,
513  .dwarf_number = 0,
514  .encoding = 28,
515  .is_virtual = false,
516  },
517  {
518  .name = "sp",
519  .cls = &mips_reg_classes[CLASS_mips_gp],
520  .single_req = &mips_single_reg_req_gp_sp,
521  .index = REG_GP_SP,
522  .global_index = REG_SP,
523  .dwarf_number = 0,
524  .encoding = 29,
525  .is_virtual = false,
526  },
527  {
528  .name = "s8",
529  .cls = &mips_reg_classes[CLASS_mips_gp],
530  .single_req = &mips_single_reg_req_gp_s8,
531  .index = REG_GP_S8,
532  .global_index = REG_S8,
533  .dwarf_number = 0,
534  .encoding = 30,
535  .is_virtual = false,
536  },
537  {
538  .name = "ra",
539  .cls = &mips_reg_classes[CLASS_mips_gp],
540  .single_req = &mips_single_reg_req_gp_ra,
541  .index = REG_GP_RA,
542  .global_index = REG_RA,
543  .dwarf_number = 0,
544  .encoding = 31,
545  .is_virtual = false,
546  },
547 
548 };
549 
553 void mips_register_init(void)
554 {
555  mips_reg_classes[CLASS_mips_gp].mode = mode_Iu;
556 
557 }
ir_mode * mode_Iu
uint32
Definition: irmode.h:187