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gen_sparc_regalloc_if.c
1 
11 #include "gen_sparc_regalloc_if.h"
12 
13 #include "sparc_bearch_t.h"
14 
15 const arch_register_req_t sparc_class_reg_req_flags = {
16  .cls = &sparc_reg_classes[CLASS_sparc_flags],
17  .width = 1,
18 };
19 static const unsigned sparc_limited_flags_psr[] = { (1U << REG_FLAGS_PSR) };
20 const arch_register_req_t sparc_single_reg_req_flags_psr = {
21  .cls = &sparc_reg_classes[CLASS_sparc_flags],
22  .limited = sparc_limited_flags_psr,
23  .width = 1,
24 };
25 const arch_register_req_t sparc_class_reg_req_fp = {
26  .cls = &sparc_reg_classes[CLASS_sparc_fp],
27  .width = 1,
28 };
29 static const unsigned sparc_limited_fp_f0[] = { (1U << REG_FP_F0) };
30 const arch_register_req_t sparc_single_reg_req_fp_f0 = {
31  .cls = &sparc_reg_classes[CLASS_sparc_fp],
32  .limited = sparc_limited_fp_f0,
33  .width = 1,
34 };
35 static const unsigned sparc_limited_fp_f1[] = { (1U << REG_FP_F1) };
36 const arch_register_req_t sparc_single_reg_req_fp_f1 = {
37  .cls = &sparc_reg_classes[CLASS_sparc_fp],
38  .limited = sparc_limited_fp_f1,
39  .width = 1,
40 };
41 static const unsigned sparc_limited_fp_f2[] = { (1U << REG_FP_F2) };
42 const arch_register_req_t sparc_single_reg_req_fp_f2 = {
43  .cls = &sparc_reg_classes[CLASS_sparc_fp],
44  .limited = sparc_limited_fp_f2,
45  .width = 1,
46 };
47 static const unsigned sparc_limited_fp_f3[] = { (1U << REG_FP_F3) };
48 const arch_register_req_t sparc_single_reg_req_fp_f3 = {
49  .cls = &sparc_reg_classes[CLASS_sparc_fp],
50  .limited = sparc_limited_fp_f3,
51  .width = 1,
52 };
53 static const unsigned sparc_limited_fp_f4[] = { (1U << REG_FP_F4) };
54 const arch_register_req_t sparc_single_reg_req_fp_f4 = {
55  .cls = &sparc_reg_classes[CLASS_sparc_fp],
56  .limited = sparc_limited_fp_f4,
57  .width = 1,
58 };
59 static const unsigned sparc_limited_fp_f5[] = { (1U << REG_FP_F5) };
60 const arch_register_req_t sparc_single_reg_req_fp_f5 = {
61  .cls = &sparc_reg_classes[CLASS_sparc_fp],
62  .limited = sparc_limited_fp_f5,
63  .width = 1,
64 };
65 static const unsigned sparc_limited_fp_f6[] = { (1U << REG_FP_F6) };
66 const arch_register_req_t sparc_single_reg_req_fp_f6 = {
67  .cls = &sparc_reg_classes[CLASS_sparc_fp],
68  .limited = sparc_limited_fp_f6,
69  .width = 1,
70 };
71 static const unsigned sparc_limited_fp_f7[] = { (1U << REG_FP_F7) };
72 const arch_register_req_t sparc_single_reg_req_fp_f7 = {
73  .cls = &sparc_reg_classes[CLASS_sparc_fp],
74  .limited = sparc_limited_fp_f7,
75  .width = 1,
76 };
77 static const unsigned sparc_limited_fp_f8[] = { (1U << REG_FP_F8) };
78 const arch_register_req_t sparc_single_reg_req_fp_f8 = {
79  .cls = &sparc_reg_classes[CLASS_sparc_fp],
80  .limited = sparc_limited_fp_f8,
81  .width = 1,
82 };
83 static const unsigned sparc_limited_fp_f9[] = { (1U << REG_FP_F9) };
84 const arch_register_req_t sparc_single_reg_req_fp_f9 = {
85  .cls = &sparc_reg_classes[CLASS_sparc_fp],
86  .limited = sparc_limited_fp_f9,
87  .width = 1,
88 };
89 static const unsigned sparc_limited_fp_f10[] = { (1U << REG_FP_F10) };
90 const arch_register_req_t sparc_single_reg_req_fp_f10 = {
91  .cls = &sparc_reg_classes[CLASS_sparc_fp],
92  .limited = sparc_limited_fp_f10,
93  .width = 1,
94 };
95 static const unsigned sparc_limited_fp_f11[] = { (1U << REG_FP_F11) };
96 const arch_register_req_t sparc_single_reg_req_fp_f11 = {
97  .cls = &sparc_reg_classes[CLASS_sparc_fp],
98  .limited = sparc_limited_fp_f11,
99  .width = 1,
100 };
101 static const unsigned sparc_limited_fp_f12[] = { (1U << REG_FP_F12) };
102 const arch_register_req_t sparc_single_reg_req_fp_f12 = {
103  .cls = &sparc_reg_classes[CLASS_sparc_fp],
104  .limited = sparc_limited_fp_f12,
105  .width = 1,
106 };
107 static const unsigned sparc_limited_fp_f13[] = { (1U << REG_FP_F13) };
108 const arch_register_req_t sparc_single_reg_req_fp_f13 = {
109  .cls = &sparc_reg_classes[CLASS_sparc_fp],
110  .limited = sparc_limited_fp_f13,
111  .width = 1,
112 };
113 static const unsigned sparc_limited_fp_f14[] = { (1U << REG_FP_F14) };
114 const arch_register_req_t sparc_single_reg_req_fp_f14 = {
115  .cls = &sparc_reg_classes[CLASS_sparc_fp],
116  .limited = sparc_limited_fp_f14,
117  .width = 1,
118 };
119 static const unsigned sparc_limited_fp_f15[] = { (1U << REG_FP_F15) };
120 const arch_register_req_t sparc_single_reg_req_fp_f15 = {
121  .cls = &sparc_reg_classes[CLASS_sparc_fp],
122  .limited = sparc_limited_fp_f15,
123  .width = 1,
124 };
125 static const unsigned sparc_limited_fp_f16[] = { (1U << REG_FP_F16) };
126 const arch_register_req_t sparc_single_reg_req_fp_f16 = {
127  .cls = &sparc_reg_classes[CLASS_sparc_fp],
128  .limited = sparc_limited_fp_f16,
129  .width = 1,
130 };
131 static const unsigned sparc_limited_fp_f17[] = { (1U << REG_FP_F17) };
132 const arch_register_req_t sparc_single_reg_req_fp_f17 = {
133  .cls = &sparc_reg_classes[CLASS_sparc_fp],
134  .limited = sparc_limited_fp_f17,
135  .width = 1,
136 };
137 static const unsigned sparc_limited_fp_f18[] = { (1U << REG_FP_F18) };
138 const arch_register_req_t sparc_single_reg_req_fp_f18 = {
139  .cls = &sparc_reg_classes[CLASS_sparc_fp],
140  .limited = sparc_limited_fp_f18,
141  .width = 1,
142 };
143 static const unsigned sparc_limited_fp_f19[] = { (1U << REG_FP_F19) };
144 const arch_register_req_t sparc_single_reg_req_fp_f19 = {
145  .cls = &sparc_reg_classes[CLASS_sparc_fp],
146  .limited = sparc_limited_fp_f19,
147  .width = 1,
148 };
149 static const unsigned sparc_limited_fp_f20[] = { (1U << REG_FP_F20) };
150 const arch_register_req_t sparc_single_reg_req_fp_f20 = {
151  .cls = &sparc_reg_classes[CLASS_sparc_fp],
152  .limited = sparc_limited_fp_f20,
153  .width = 1,
154 };
155 static const unsigned sparc_limited_fp_f21[] = { (1U << REG_FP_F21) };
156 const arch_register_req_t sparc_single_reg_req_fp_f21 = {
157  .cls = &sparc_reg_classes[CLASS_sparc_fp],
158  .limited = sparc_limited_fp_f21,
159  .width = 1,
160 };
161 static const unsigned sparc_limited_fp_f22[] = { (1U << REG_FP_F22) };
162 const arch_register_req_t sparc_single_reg_req_fp_f22 = {
163  .cls = &sparc_reg_classes[CLASS_sparc_fp],
164  .limited = sparc_limited_fp_f22,
165  .width = 1,
166 };
167 static const unsigned sparc_limited_fp_f23[] = { (1U << REG_FP_F23) };
168 const arch_register_req_t sparc_single_reg_req_fp_f23 = {
169  .cls = &sparc_reg_classes[CLASS_sparc_fp],
170  .limited = sparc_limited_fp_f23,
171  .width = 1,
172 };
173 static const unsigned sparc_limited_fp_f24[] = { (1U << REG_FP_F24) };
174 const arch_register_req_t sparc_single_reg_req_fp_f24 = {
175  .cls = &sparc_reg_classes[CLASS_sparc_fp],
176  .limited = sparc_limited_fp_f24,
177  .width = 1,
178 };
179 static const unsigned sparc_limited_fp_f25[] = { (1U << REG_FP_F25) };
180 const arch_register_req_t sparc_single_reg_req_fp_f25 = {
181  .cls = &sparc_reg_classes[CLASS_sparc_fp],
182  .limited = sparc_limited_fp_f25,
183  .width = 1,
184 };
185 static const unsigned sparc_limited_fp_f26[] = { (1U << REG_FP_F26) };
186 const arch_register_req_t sparc_single_reg_req_fp_f26 = {
187  .cls = &sparc_reg_classes[CLASS_sparc_fp],
188  .limited = sparc_limited_fp_f26,
189  .width = 1,
190 };
191 static const unsigned sparc_limited_fp_f27[] = { (1U << REG_FP_F27) };
192 const arch_register_req_t sparc_single_reg_req_fp_f27 = {
193  .cls = &sparc_reg_classes[CLASS_sparc_fp],
194  .limited = sparc_limited_fp_f27,
195  .width = 1,
196 };
197 static const unsigned sparc_limited_fp_f28[] = { (1U << REG_FP_F28) };
198 const arch_register_req_t sparc_single_reg_req_fp_f28 = {
199  .cls = &sparc_reg_classes[CLASS_sparc_fp],
200  .limited = sparc_limited_fp_f28,
201  .width = 1,
202 };
203 static const unsigned sparc_limited_fp_f29[] = { (1U << REG_FP_F29) };
204 const arch_register_req_t sparc_single_reg_req_fp_f29 = {
205  .cls = &sparc_reg_classes[CLASS_sparc_fp],
206  .limited = sparc_limited_fp_f29,
207  .width = 1,
208 };
209 static const unsigned sparc_limited_fp_f30[] = { (1U << REG_FP_F30) };
210 const arch_register_req_t sparc_single_reg_req_fp_f30 = {
211  .cls = &sparc_reg_classes[CLASS_sparc_fp],
212  .limited = sparc_limited_fp_f30,
213  .width = 1,
214 };
215 static const unsigned sparc_limited_fp_f31[] = { (1U << REG_FP_F31) };
216 const arch_register_req_t sparc_single_reg_req_fp_f31 = {
217  .cls = &sparc_reg_classes[CLASS_sparc_fp],
218  .limited = sparc_limited_fp_f31,
219  .width = 1,
220 };
221 const arch_register_req_t sparc_class_reg_req_fpflags = {
222  .cls = &sparc_reg_classes[CLASS_sparc_fpflags],
223  .width = 1,
224 };
225 static const unsigned sparc_limited_fpflags_fsr[] = { (1U << REG_FPFLAGS_FSR) };
226 const arch_register_req_t sparc_single_reg_req_fpflags_fsr = {
227  .cls = &sparc_reg_classes[CLASS_sparc_fpflags],
228  .limited = sparc_limited_fpflags_fsr,
229  .width = 1,
230 };
231 const arch_register_req_t sparc_class_reg_req_gp = {
232  .cls = &sparc_reg_classes[CLASS_sparc_gp],
233  .width = 1,
234 };
235 static const unsigned sparc_limited_gp_l0[] = { (1U << REG_GP_L0) };
236 const arch_register_req_t sparc_single_reg_req_gp_l0 = {
237  .cls = &sparc_reg_classes[CLASS_sparc_gp],
238  .limited = sparc_limited_gp_l0,
239  .width = 1,
240 };
241 static const unsigned sparc_limited_gp_l1[] = { (1U << REG_GP_L1) };
242 const arch_register_req_t sparc_single_reg_req_gp_l1 = {
243  .cls = &sparc_reg_classes[CLASS_sparc_gp],
244  .limited = sparc_limited_gp_l1,
245  .width = 1,
246 };
247 static const unsigned sparc_limited_gp_l2[] = { (1U << REG_GP_L2) };
248 const arch_register_req_t sparc_single_reg_req_gp_l2 = {
249  .cls = &sparc_reg_classes[CLASS_sparc_gp],
250  .limited = sparc_limited_gp_l2,
251  .width = 1,
252 };
253 static const unsigned sparc_limited_gp_l3[] = { (1U << REG_GP_L3) };
254 const arch_register_req_t sparc_single_reg_req_gp_l3 = {
255  .cls = &sparc_reg_classes[CLASS_sparc_gp],
256  .limited = sparc_limited_gp_l3,
257  .width = 1,
258 };
259 static const unsigned sparc_limited_gp_l4[] = { (1U << REG_GP_L4) };
260 const arch_register_req_t sparc_single_reg_req_gp_l4 = {
261  .cls = &sparc_reg_classes[CLASS_sparc_gp],
262  .limited = sparc_limited_gp_l4,
263  .width = 1,
264 };
265 static const unsigned sparc_limited_gp_l5[] = { (1U << REG_GP_L5) };
266 const arch_register_req_t sparc_single_reg_req_gp_l5 = {
267  .cls = &sparc_reg_classes[CLASS_sparc_gp],
268  .limited = sparc_limited_gp_l5,
269  .width = 1,
270 };
271 static const unsigned sparc_limited_gp_l6[] = { (1U << REG_GP_L6) };
272 const arch_register_req_t sparc_single_reg_req_gp_l6 = {
273  .cls = &sparc_reg_classes[CLASS_sparc_gp],
274  .limited = sparc_limited_gp_l6,
275  .width = 1,
276 };
277 static const unsigned sparc_limited_gp_l7[] = { (1U << REG_GP_L7) };
278 const arch_register_req_t sparc_single_reg_req_gp_l7 = {
279  .cls = &sparc_reg_classes[CLASS_sparc_gp],
280  .limited = sparc_limited_gp_l7,
281  .width = 1,
282 };
283 static const unsigned sparc_limited_gp_g0[] = { (1U << REG_GP_G0) };
284 const arch_register_req_t sparc_single_reg_req_gp_g0 = {
285  .cls = &sparc_reg_classes[CLASS_sparc_gp],
286  .limited = sparc_limited_gp_g0,
287  .width = 1,
288 };
289 static const unsigned sparc_limited_gp_g1[] = { (1U << REG_GP_G1) };
290 const arch_register_req_t sparc_single_reg_req_gp_g1 = {
291  .cls = &sparc_reg_classes[CLASS_sparc_gp],
292  .limited = sparc_limited_gp_g1,
293  .width = 1,
294 };
295 static const unsigned sparc_limited_gp_g2[] = { (1U << REG_GP_G2) };
296 const arch_register_req_t sparc_single_reg_req_gp_g2 = {
297  .cls = &sparc_reg_classes[CLASS_sparc_gp],
298  .limited = sparc_limited_gp_g2,
299  .width = 1,
300 };
301 static const unsigned sparc_limited_gp_g3[] = { (1U << REG_GP_G3) };
302 const arch_register_req_t sparc_single_reg_req_gp_g3 = {
303  .cls = &sparc_reg_classes[CLASS_sparc_gp],
304  .limited = sparc_limited_gp_g3,
305  .width = 1,
306 };
307 static const unsigned sparc_limited_gp_g4[] = { (1U << REG_GP_G4) };
308 const arch_register_req_t sparc_single_reg_req_gp_g4 = {
309  .cls = &sparc_reg_classes[CLASS_sparc_gp],
310  .limited = sparc_limited_gp_g4,
311  .width = 1,
312 };
313 static const unsigned sparc_limited_gp_g5[] = { (1U << REG_GP_G5) };
314 const arch_register_req_t sparc_single_reg_req_gp_g5 = {
315  .cls = &sparc_reg_classes[CLASS_sparc_gp],
316  .limited = sparc_limited_gp_g5,
317  .width = 1,
318 };
319 static const unsigned sparc_limited_gp_g6[] = { (1U << REG_GP_G6) };
320 const arch_register_req_t sparc_single_reg_req_gp_g6 = {
321  .cls = &sparc_reg_classes[CLASS_sparc_gp],
322  .limited = sparc_limited_gp_g6,
323  .width = 1,
324 };
325 static const unsigned sparc_limited_gp_g7[] = { (1U << REG_GP_G7) };
326 const arch_register_req_t sparc_single_reg_req_gp_g7 = {
327  .cls = &sparc_reg_classes[CLASS_sparc_gp],
328  .limited = sparc_limited_gp_g7,
329  .width = 1,
330 };
331 static const unsigned sparc_limited_gp_o0[] = { (1U << REG_GP_O0) };
332 const arch_register_req_t sparc_single_reg_req_gp_o0 = {
333  .cls = &sparc_reg_classes[CLASS_sparc_gp],
334  .limited = sparc_limited_gp_o0,
335  .width = 1,
336 };
337 static const unsigned sparc_limited_gp_o1[] = { (1U << REG_GP_O1) };
338 const arch_register_req_t sparc_single_reg_req_gp_o1 = {
339  .cls = &sparc_reg_classes[CLASS_sparc_gp],
340  .limited = sparc_limited_gp_o1,
341  .width = 1,
342 };
343 static const unsigned sparc_limited_gp_o2[] = { (1U << REG_GP_O2) };
344 const arch_register_req_t sparc_single_reg_req_gp_o2 = {
345  .cls = &sparc_reg_classes[CLASS_sparc_gp],
346  .limited = sparc_limited_gp_o2,
347  .width = 1,
348 };
349 static const unsigned sparc_limited_gp_o3[] = { (1U << REG_GP_O3) };
350 const arch_register_req_t sparc_single_reg_req_gp_o3 = {
351  .cls = &sparc_reg_classes[CLASS_sparc_gp],
352  .limited = sparc_limited_gp_o3,
353  .width = 1,
354 };
355 static const unsigned sparc_limited_gp_o4[] = { (1U << REG_GP_O4) };
356 const arch_register_req_t sparc_single_reg_req_gp_o4 = {
357  .cls = &sparc_reg_classes[CLASS_sparc_gp],
358  .limited = sparc_limited_gp_o4,
359  .width = 1,
360 };
361 static const unsigned sparc_limited_gp_o5[] = { (1U << REG_GP_O5) };
362 const arch_register_req_t sparc_single_reg_req_gp_o5 = {
363  .cls = &sparc_reg_classes[CLASS_sparc_gp],
364  .limited = sparc_limited_gp_o5,
365  .width = 1,
366 };
367 static const unsigned sparc_limited_gp_sp[] = { (1U << REG_GP_SP) };
368 const arch_register_req_t sparc_single_reg_req_gp_sp = {
369  .cls = &sparc_reg_classes[CLASS_sparc_gp],
370  .limited = sparc_limited_gp_sp,
371  .width = 1,
372 };
373 static const unsigned sparc_limited_gp_o7[] = { (1U << REG_GP_O7) };
374 const arch_register_req_t sparc_single_reg_req_gp_o7 = {
375  .cls = &sparc_reg_classes[CLASS_sparc_gp],
376  .limited = sparc_limited_gp_o7,
377  .width = 1,
378 };
379 static const unsigned sparc_limited_gp_i0[] = { (1U << REG_GP_I0) };
380 const arch_register_req_t sparc_single_reg_req_gp_i0 = {
381  .cls = &sparc_reg_classes[CLASS_sparc_gp],
382  .limited = sparc_limited_gp_i0,
383  .width = 1,
384 };
385 static const unsigned sparc_limited_gp_i1[] = { (1U << REG_GP_I1) };
386 const arch_register_req_t sparc_single_reg_req_gp_i1 = {
387  .cls = &sparc_reg_classes[CLASS_sparc_gp],
388  .limited = sparc_limited_gp_i1,
389  .width = 1,
390 };
391 static const unsigned sparc_limited_gp_i2[] = { (1U << REG_GP_I2) };
392 const arch_register_req_t sparc_single_reg_req_gp_i2 = {
393  .cls = &sparc_reg_classes[CLASS_sparc_gp],
394  .limited = sparc_limited_gp_i2,
395  .width = 1,
396 };
397 static const unsigned sparc_limited_gp_i3[] = { (1U << REG_GP_I3) };
398 const arch_register_req_t sparc_single_reg_req_gp_i3 = {
399  .cls = &sparc_reg_classes[CLASS_sparc_gp],
400  .limited = sparc_limited_gp_i3,
401  .width = 1,
402 };
403 static const unsigned sparc_limited_gp_i4[] = { (1U << REG_GP_I4) };
404 const arch_register_req_t sparc_single_reg_req_gp_i4 = {
405  .cls = &sparc_reg_classes[CLASS_sparc_gp],
406  .limited = sparc_limited_gp_i4,
407  .width = 1,
408 };
409 static const unsigned sparc_limited_gp_i5[] = { (1U << REG_GP_I5) };
410 const arch_register_req_t sparc_single_reg_req_gp_i5 = {
411  .cls = &sparc_reg_classes[CLASS_sparc_gp],
412  .limited = sparc_limited_gp_i5,
413  .width = 1,
414 };
415 static const unsigned sparc_limited_gp_fp[] = { (1U << REG_GP_FP) };
416 const arch_register_req_t sparc_single_reg_req_gp_fp = {
417  .cls = &sparc_reg_classes[CLASS_sparc_gp],
418  .limited = sparc_limited_gp_fp,
419  .width = 1,
420 };
421 static const unsigned sparc_limited_gp_i7[] = { (1U << REG_GP_I7) };
422 const arch_register_req_t sparc_single_reg_req_gp_i7 = {
423  .cls = &sparc_reg_classes[CLASS_sparc_gp],
424  .limited = sparc_limited_gp_i7,
425  .width = 1,
426 };
427 const arch_register_req_t sparc_class_reg_req_mul_div_high_res = {
428  .cls = &sparc_reg_classes[CLASS_sparc_mul_div_high_res],
429  .width = 1,
430 };
431 static const unsigned sparc_limited_mul_div_high_res_y[] = { (1U << REG_MUL_DIV_HIGH_RES_Y) };
432 const arch_register_req_t sparc_single_reg_req_mul_div_high_res_y = {
433  .cls = &sparc_reg_classes[CLASS_sparc_mul_div_high_res],
434  .limited = sparc_limited_mul_div_high_res_y,
435  .width = 1,
436 };
437 
438 
439 arch_register_class_t sparc_reg_classes[] = {
440  {
441  .name = "sparc_flags",
442  .mode = NULL,
443  .regs = &sparc_registers[REG_PSR],
444  .class_req = &sparc_class_reg_req_flags,
445  .index = CLASS_sparc_flags,
446  .n_regs = 1,
447  .manual_ra = true,
448  },
449  {
450  .name = "sparc_fp",
451  .mode = NULL,
452  .regs = &sparc_registers[REG_F0],
453  .class_req = &sparc_class_reg_req_fp,
454  .index = CLASS_sparc_fp,
455  .n_regs = 32,
456  },
457  {
458  .name = "sparc_fpflags",
459  .mode = NULL,
460  .regs = &sparc_registers[REG_FSR],
461  .class_req = &sparc_class_reg_req_fpflags,
462  .index = CLASS_sparc_fpflags,
463  .n_regs = 1,
464  .manual_ra = true,
465  },
466  {
467  .name = "sparc_gp",
468  .mode = NULL,
469  .regs = &sparc_registers[REG_L0],
470  .class_req = &sparc_class_reg_req_gp,
471  .index = CLASS_sparc_gp,
472  .n_regs = 32,
473  },
474  {
475  .name = "sparc_mul_div_high_res",
476  .mode = NULL,
477  .regs = &sparc_registers[REG_Y],
478  .class_req = &sparc_class_reg_req_mul_div_high_res,
479  .index = CLASS_sparc_mul_div_high_res,
480  .n_regs = 1,
481  .manual_ra = true,
482  },
483 
484 };
485 
487 const arch_register_t sparc_registers[] = {
488  {
489  .name = "psr",
490  .cls = &sparc_reg_classes[CLASS_sparc_flags],
491  .single_req = &sparc_single_reg_req_flags_psr,
492  .index = REG_FLAGS_PSR,
493  .global_index = REG_PSR,
494  .dwarf_number = 0,
495  .encoding = REG_FLAGS_PSR,
496  .is_virtual = false,
497  },
498  {
499  .name = "f0",
500  .cls = &sparc_reg_classes[CLASS_sparc_fp],
501  .single_req = &sparc_single_reg_req_fp_f0,
502  .index = REG_FP_F0,
503  .global_index = REG_F0,
504  .dwarf_number = 32,
505  .encoding = 0,
506  .is_virtual = false,
507  },
508  {
509  .name = "f1",
510  .cls = &sparc_reg_classes[CLASS_sparc_fp],
511  .single_req = &sparc_single_reg_req_fp_f1,
512  .index = REG_FP_F1,
513  .global_index = REG_F1,
514  .dwarf_number = 33,
515  .encoding = 1,
516  .is_virtual = false,
517  },
518  {
519  .name = "f2",
520  .cls = &sparc_reg_classes[CLASS_sparc_fp],
521  .single_req = &sparc_single_reg_req_fp_f2,
522  .index = REG_FP_F2,
523  .global_index = REG_F2,
524  .dwarf_number = 34,
525  .encoding = 2,
526  .is_virtual = false,
527  },
528  {
529  .name = "f3",
530  .cls = &sparc_reg_classes[CLASS_sparc_fp],
531  .single_req = &sparc_single_reg_req_fp_f3,
532  .index = REG_FP_F3,
533  .global_index = REG_F3,
534  .dwarf_number = 35,
535  .encoding = 3,
536  .is_virtual = false,
537  },
538  {
539  .name = "f4",
540  .cls = &sparc_reg_classes[CLASS_sparc_fp],
541  .single_req = &sparc_single_reg_req_fp_f4,
542  .index = REG_FP_F4,
543  .global_index = REG_F4,
544  .dwarf_number = 36,
545  .encoding = 4,
546  .is_virtual = false,
547  },
548  {
549  .name = "f5",
550  .cls = &sparc_reg_classes[CLASS_sparc_fp],
551  .single_req = &sparc_single_reg_req_fp_f5,
552  .index = REG_FP_F5,
553  .global_index = REG_F5,
554  .dwarf_number = 37,
555  .encoding = 5,
556  .is_virtual = false,
557  },
558  {
559  .name = "f6",
560  .cls = &sparc_reg_classes[CLASS_sparc_fp],
561  .single_req = &sparc_single_reg_req_fp_f6,
562  .index = REG_FP_F6,
563  .global_index = REG_F6,
564  .dwarf_number = 38,
565  .encoding = 6,
566  .is_virtual = false,
567  },
568  {
569  .name = "f7",
570  .cls = &sparc_reg_classes[CLASS_sparc_fp],
571  .single_req = &sparc_single_reg_req_fp_f7,
572  .index = REG_FP_F7,
573  .global_index = REG_F7,
574  .dwarf_number = 39,
575  .encoding = 7,
576  .is_virtual = false,
577  },
578  {
579  .name = "f8",
580  .cls = &sparc_reg_classes[CLASS_sparc_fp],
581  .single_req = &sparc_single_reg_req_fp_f8,
582  .index = REG_FP_F8,
583  .global_index = REG_F8,
584  .dwarf_number = 40,
585  .encoding = 8,
586  .is_virtual = false,
587  },
588  {
589  .name = "f9",
590  .cls = &sparc_reg_classes[CLASS_sparc_fp],
591  .single_req = &sparc_single_reg_req_fp_f9,
592  .index = REG_FP_F9,
593  .global_index = REG_F9,
594  .dwarf_number = 41,
595  .encoding = 9,
596  .is_virtual = false,
597  },
598  {
599  .name = "f10",
600  .cls = &sparc_reg_classes[CLASS_sparc_fp],
601  .single_req = &sparc_single_reg_req_fp_f10,
602  .index = REG_FP_F10,
603  .global_index = REG_F10,
604  .dwarf_number = 42,
605  .encoding = 10,
606  .is_virtual = false,
607  },
608  {
609  .name = "f11",
610  .cls = &sparc_reg_classes[CLASS_sparc_fp],
611  .single_req = &sparc_single_reg_req_fp_f11,
612  .index = REG_FP_F11,
613  .global_index = REG_F11,
614  .dwarf_number = 43,
615  .encoding = 11,
616  .is_virtual = false,
617  },
618  {
619  .name = "f12",
620  .cls = &sparc_reg_classes[CLASS_sparc_fp],
621  .single_req = &sparc_single_reg_req_fp_f12,
622  .index = REG_FP_F12,
623  .global_index = REG_F12,
624  .dwarf_number = 44,
625  .encoding = 12,
626  .is_virtual = false,
627  },
628  {
629  .name = "f13",
630  .cls = &sparc_reg_classes[CLASS_sparc_fp],
631  .single_req = &sparc_single_reg_req_fp_f13,
632  .index = REG_FP_F13,
633  .global_index = REG_F13,
634  .dwarf_number = 45,
635  .encoding = 13,
636  .is_virtual = false,
637  },
638  {
639  .name = "f14",
640  .cls = &sparc_reg_classes[CLASS_sparc_fp],
641  .single_req = &sparc_single_reg_req_fp_f14,
642  .index = REG_FP_F14,
643  .global_index = REG_F14,
644  .dwarf_number = 46,
645  .encoding = 14,
646  .is_virtual = false,
647  },
648  {
649  .name = "f15",
650  .cls = &sparc_reg_classes[CLASS_sparc_fp],
651  .single_req = &sparc_single_reg_req_fp_f15,
652  .index = REG_FP_F15,
653  .global_index = REG_F15,
654  .dwarf_number = 47,
655  .encoding = 15,
656  .is_virtual = false,
657  },
658  {
659  .name = "f16",
660  .cls = &sparc_reg_classes[CLASS_sparc_fp],
661  .single_req = &sparc_single_reg_req_fp_f16,
662  .index = REG_FP_F16,
663  .global_index = REG_F16,
664  .dwarf_number = 48,
665  .encoding = 16,
666  .is_virtual = false,
667  },
668  {
669  .name = "f17",
670  .cls = &sparc_reg_classes[CLASS_sparc_fp],
671  .single_req = &sparc_single_reg_req_fp_f17,
672  .index = REG_FP_F17,
673  .global_index = REG_F17,
674  .dwarf_number = 49,
675  .encoding = 17,
676  .is_virtual = false,
677  },
678  {
679  .name = "f18",
680  .cls = &sparc_reg_classes[CLASS_sparc_fp],
681  .single_req = &sparc_single_reg_req_fp_f18,
682  .index = REG_FP_F18,
683  .global_index = REG_F18,
684  .dwarf_number = 50,
685  .encoding = 18,
686  .is_virtual = false,
687  },
688  {
689  .name = "f19",
690  .cls = &sparc_reg_classes[CLASS_sparc_fp],
691  .single_req = &sparc_single_reg_req_fp_f19,
692  .index = REG_FP_F19,
693  .global_index = REG_F19,
694  .dwarf_number = 51,
695  .encoding = 19,
696  .is_virtual = false,
697  },
698  {
699  .name = "f20",
700  .cls = &sparc_reg_classes[CLASS_sparc_fp],
701  .single_req = &sparc_single_reg_req_fp_f20,
702  .index = REG_FP_F20,
703  .global_index = REG_F20,
704  .dwarf_number = 52,
705  .encoding = 20,
706  .is_virtual = false,
707  },
708  {
709  .name = "f21",
710  .cls = &sparc_reg_classes[CLASS_sparc_fp],
711  .single_req = &sparc_single_reg_req_fp_f21,
712  .index = REG_FP_F21,
713  .global_index = REG_F21,
714  .dwarf_number = 53,
715  .encoding = 21,
716  .is_virtual = false,
717  },
718  {
719  .name = "f22",
720  .cls = &sparc_reg_classes[CLASS_sparc_fp],
721  .single_req = &sparc_single_reg_req_fp_f22,
722  .index = REG_FP_F22,
723  .global_index = REG_F22,
724  .dwarf_number = 54,
725  .encoding = 22,
726  .is_virtual = false,
727  },
728  {
729  .name = "f23",
730  .cls = &sparc_reg_classes[CLASS_sparc_fp],
731  .single_req = &sparc_single_reg_req_fp_f23,
732  .index = REG_FP_F23,
733  .global_index = REG_F23,
734  .dwarf_number = 55,
735  .encoding = 23,
736  .is_virtual = false,
737  },
738  {
739  .name = "f24",
740  .cls = &sparc_reg_classes[CLASS_sparc_fp],
741  .single_req = &sparc_single_reg_req_fp_f24,
742  .index = REG_FP_F24,
743  .global_index = REG_F24,
744  .dwarf_number = 56,
745  .encoding = 24,
746  .is_virtual = false,
747  },
748  {
749  .name = "f25",
750  .cls = &sparc_reg_classes[CLASS_sparc_fp],
751  .single_req = &sparc_single_reg_req_fp_f25,
752  .index = REG_FP_F25,
753  .global_index = REG_F25,
754  .dwarf_number = 57,
755  .encoding = 25,
756  .is_virtual = false,
757  },
758  {
759  .name = "f26",
760  .cls = &sparc_reg_classes[CLASS_sparc_fp],
761  .single_req = &sparc_single_reg_req_fp_f26,
762  .index = REG_FP_F26,
763  .global_index = REG_F26,
764  .dwarf_number = 58,
765  .encoding = 26,
766  .is_virtual = false,
767  },
768  {
769  .name = "f27",
770  .cls = &sparc_reg_classes[CLASS_sparc_fp],
771  .single_req = &sparc_single_reg_req_fp_f27,
772  .index = REG_FP_F27,
773  .global_index = REG_F27,
774  .dwarf_number = 59,
775  .encoding = 27,
776  .is_virtual = false,
777  },
778  {
779  .name = "f28",
780  .cls = &sparc_reg_classes[CLASS_sparc_fp],
781  .single_req = &sparc_single_reg_req_fp_f28,
782  .index = REG_FP_F28,
783  .global_index = REG_F28,
784  .dwarf_number = 60,
785  .encoding = 28,
786  .is_virtual = false,
787  },
788  {
789  .name = "f29",
790  .cls = &sparc_reg_classes[CLASS_sparc_fp],
791  .single_req = &sparc_single_reg_req_fp_f29,
792  .index = REG_FP_F29,
793  .global_index = REG_F29,
794  .dwarf_number = 61,
795  .encoding = 29,
796  .is_virtual = false,
797  },
798  {
799  .name = "f30",
800  .cls = &sparc_reg_classes[CLASS_sparc_fp],
801  .single_req = &sparc_single_reg_req_fp_f30,
802  .index = REG_FP_F30,
803  .global_index = REG_F30,
804  .dwarf_number = 62,
805  .encoding = 30,
806  .is_virtual = false,
807  },
808  {
809  .name = "f31",
810  .cls = &sparc_reg_classes[CLASS_sparc_fp],
811  .single_req = &sparc_single_reg_req_fp_f31,
812  .index = REG_FP_F31,
813  .global_index = REG_F31,
814  .dwarf_number = 63,
815  .encoding = 31,
816  .is_virtual = false,
817  },
818  {
819  .name = "fsr",
820  .cls = &sparc_reg_classes[CLASS_sparc_fpflags],
821  .single_req = &sparc_single_reg_req_fpflags_fsr,
822  .index = REG_FPFLAGS_FSR,
823  .global_index = REG_FSR,
824  .dwarf_number = 0,
825  .encoding = REG_FPFLAGS_FSR,
826  .is_virtual = false,
827  },
828  {
829  .name = "l0",
830  .cls = &sparc_reg_classes[CLASS_sparc_gp],
831  .single_req = &sparc_single_reg_req_gp_l0,
832  .index = REG_GP_L0,
833  .global_index = REG_L0,
834  .dwarf_number = 16,
835  .encoding = 16,
836  .is_virtual = false,
837  },
838  {
839  .name = "l1",
840  .cls = &sparc_reg_classes[CLASS_sparc_gp],
841  .single_req = &sparc_single_reg_req_gp_l1,
842  .index = REG_GP_L1,
843  .global_index = REG_L1,
844  .dwarf_number = 17,
845  .encoding = 17,
846  .is_virtual = false,
847  },
848  {
849  .name = "l2",
850  .cls = &sparc_reg_classes[CLASS_sparc_gp],
851  .single_req = &sparc_single_reg_req_gp_l2,
852  .index = REG_GP_L2,
853  .global_index = REG_L2,
854  .dwarf_number = 18,
855  .encoding = 18,
856  .is_virtual = false,
857  },
858  {
859  .name = "l3",
860  .cls = &sparc_reg_classes[CLASS_sparc_gp],
861  .single_req = &sparc_single_reg_req_gp_l3,
862  .index = REG_GP_L3,
863  .global_index = REG_L3,
864  .dwarf_number = 19,
865  .encoding = 19,
866  .is_virtual = false,
867  },
868  {
869  .name = "l4",
870  .cls = &sparc_reg_classes[CLASS_sparc_gp],
871  .single_req = &sparc_single_reg_req_gp_l4,
872  .index = REG_GP_L4,
873  .global_index = REG_L4,
874  .dwarf_number = 20,
875  .encoding = 20,
876  .is_virtual = false,
877  },
878  {
879  .name = "l5",
880  .cls = &sparc_reg_classes[CLASS_sparc_gp],
881  .single_req = &sparc_single_reg_req_gp_l5,
882  .index = REG_GP_L5,
883  .global_index = REG_L5,
884  .dwarf_number = 21,
885  .encoding = 21,
886  .is_virtual = false,
887  },
888  {
889  .name = "l6",
890  .cls = &sparc_reg_classes[CLASS_sparc_gp],
891  .single_req = &sparc_single_reg_req_gp_l6,
892  .index = REG_GP_L6,
893  .global_index = REG_L6,
894  .dwarf_number = 22,
895  .encoding = 22,
896  .is_virtual = false,
897  },
898  {
899  .name = "l7",
900  .cls = &sparc_reg_classes[CLASS_sparc_gp],
901  .single_req = &sparc_single_reg_req_gp_l7,
902  .index = REG_GP_L7,
903  .global_index = REG_L7,
904  .dwarf_number = 23,
905  .encoding = 23,
906  .is_virtual = false,
907  },
908  {
909  .name = "g0",
910  .cls = &sparc_reg_classes[CLASS_sparc_gp],
911  .single_req = &sparc_single_reg_req_gp_g0,
912  .index = REG_GP_G0,
913  .global_index = REG_G0,
914  .dwarf_number = 0,
915  .encoding = 0,
916  .is_virtual = false,
917  },
918  {
919  .name = "g1",
920  .cls = &sparc_reg_classes[CLASS_sparc_gp],
921  .single_req = &sparc_single_reg_req_gp_g1,
922  .index = REG_GP_G1,
923  .global_index = REG_G1,
924  .dwarf_number = 1,
925  .encoding = 1,
926  .is_virtual = false,
927  },
928  {
929  .name = "g2",
930  .cls = &sparc_reg_classes[CLASS_sparc_gp],
931  .single_req = &sparc_single_reg_req_gp_g2,
932  .index = REG_GP_G2,
933  .global_index = REG_G2,
934  .dwarf_number = 2,
935  .encoding = 2,
936  .is_virtual = false,
937  },
938  {
939  .name = "g3",
940  .cls = &sparc_reg_classes[CLASS_sparc_gp],
941  .single_req = &sparc_single_reg_req_gp_g3,
942  .index = REG_GP_G3,
943  .global_index = REG_G3,
944  .dwarf_number = 3,
945  .encoding = 3,
946  .is_virtual = false,
947  },
948  {
949  .name = "g4",
950  .cls = &sparc_reg_classes[CLASS_sparc_gp],
951  .single_req = &sparc_single_reg_req_gp_g4,
952  .index = REG_GP_G4,
953  .global_index = REG_G4,
954  .dwarf_number = 4,
955  .encoding = 4,
956  .is_virtual = false,
957  },
958  {
959  .name = "g5",
960  .cls = &sparc_reg_classes[CLASS_sparc_gp],
961  .single_req = &sparc_single_reg_req_gp_g5,
962  .index = REG_GP_G5,
963  .global_index = REG_G5,
964  .dwarf_number = 5,
965  .encoding = 5,
966  .is_virtual = false,
967  },
968  {
969  .name = "g6",
970  .cls = &sparc_reg_classes[CLASS_sparc_gp],
971  .single_req = &sparc_single_reg_req_gp_g6,
972  .index = REG_GP_G6,
973  .global_index = REG_G6,
974  .dwarf_number = 6,
975  .encoding = 6,
976  .is_virtual = false,
977  },
978  {
979  .name = "g7",
980  .cls = &sparc_reg_classes[CLASS_sparc_gp],
981  .single_req = &sparc_single_reg_req_gp_g7,
982  .index = REG_GP_G7,
983  .global_index = REG_G7,
984  .dwarf_number = 7,
985  .encoding = 7,
986  .is_virtual = false,
987  },
988  {
989  .name = "o0",
990  .cls = &sparc_reg_classes[CLASS_sparc_gp],
991  .single_req = &sparc_single_reg_req_gp_o0,
992  .index = REG_GP_O0,
993  .global_index = REG_O0,
994  .dwarf_number = 8,
995  .encoding = 8,
996  .is_virtual = false,
997  },
998  {
999  .name = "o1",
1000  .cls = &sparc_reg_classes[CLASS_sparc_gp],
1001  .single_req = &sparc_single_reg_req_gp_o1,
1002  .index = REG_GP_O1,
1003  .global_index = REG_O1,
1004  .dwarf_number = 9,
1005  .encoding = 9,
1006  .is_virtual = false,
1007  },
1008  {
1009  .name = "o2",
1010  .cls = &sparc_reg_classes[CLASS_sparc_gp],
1011  .single_req = &sparc_single_reg_req_gp_o2,
1012  .index = REG_GP_O2,
1013  .global_index = REG_O2,
1014  .dwarf_number = 10,
1015  .encoding = 10,
1016  .is_virtual = false,
1017  },
1018  {
1019  .name = "o3",
1020  .cls = &sparc_reg_classes[CLASS_sparc_gp],
1021  .single_req = &sparc_single_reg_req_gp_o3,
1022  .index = REG_GP_O3,
1023  .global_index = REG_O3,
1024  .dwarf_number = 11,
1025  .encoding = 11,
1026  .is_virtual = false,
1027  },
1028  {
1029  .name = "o4",
1030  .cls = &sparc_reg_classes[CLASS_sparc_gp],
1031  .single_req = &sparc_single_reg_req_gp_o4,
1032  .index = REG_GP_O4,
1033  .global_index = REG_O4,
1034  .dwarf_number = 12,
1035  .encoding = 12,
1036  .is_virtual = false,
1037  },
1038  {
1039  .name = "o5",
1040  .cls = &sparc_reg_classes[CLASS_sparc_gp],
1041  .single_req = &sparc_single_reg_req_gp_o5,
1042  .index = REG_GP_O5,
1043  .global_index = REG_O5,
1044  .dwarf_number = 13,
1045  .encoding = 13,
1046  .is_virtual = false,
1047  },
1048  {
1049  .name = "sp",
1050  .cls = &sparc_reg_classes[CLASS_sparc_gp],
1051  .single_req = &sparc_single_reg_req_gp_sp,
1052  .index = REG_GP_SP,
1053  .global_index = REG_SP,
1054  .dwarf_number = 14,
1055  .encoding = 14,
1056  .is_virtual = false,
1057  },
1058  {
1059  .name = "o7",
1060  .cls = &sparc_reg_classes[CLASS_sparc_gp],
1061  .single_req = &sparc_single_reg_req_gp_o7,
1062  .index = REG_GP_O7,
1063  .global_index = REG_O7,
1064  .dwarf_number = 15,
1065  .encoding = 15,
1066  .is_virtual = false,
1067  },
1068  {
1069  .name = "i0",
1070  .cls = &sparc_reg_classes[CLASS_sparc_gp],
1071  .single_req = &sparc_single_reg_req_gp_i0,
1072  .index = REG_GP_I0,
1073  .global_index = REG_I0,
1074  .dwarf_number = 24,
1075  .encoding = 24,
1076  .is_virtual = false,
1077  },
1078  {
1079  .name = "i1",
1080  .cls = &sparc_reg_classes[CLASS_sparc_gp],
1081  .single_req = &sparc_single_reg_req_gp_i1,
1082  .index = REG_GP_I1,
1083  .global_index = REG_I1,
1084  .dwarf_number = 25,
1085  .encoding = 25,
1086  .is_virtual = false,
1087  },
1088  {
1089  .name = "i2",
1090  .cls = &sparc_reg_classes[CLASS_sparc_gp],
1091  .single_req = &sparc_single_reg_req_gp_i2,
1092  .index = REG_GP_I2,
1093  .global_index = REG_I2,
1094  .dwarf_number = 26,
1095  .encoding = 26,
1096  .is_virtual = false,
1097  },
1098  {
1099  .name = "i3",
1100  .cls = &sparc_reg_classes[CLASS_sparc_gp],
1101  .single_req = &sparc_single_reg_req_gp_i3,
1102  .index = REG_GP_I3,
1103  .global_index = REG_I3,
1104  .dwarf_number = 27,
1105  .encoding = 27,
1106  .is_virtual = false,
1107  },
1108  {
1109  .name = "i4",
1110  .cls = &sparc_reg_classes[CLASS_sparc_gp],
1111  .single_req = &sparc_single_reg_req_gp_i4,
1112  .index = REG_GP_I4,
1113  .global_index = REG_I4,
1114  .dwarf_number = 28,
1115  .encoding = 28,
1116  .is_virtual = false,
1117  },
1118  {
1119  .name = "i5",
1120  .cls = &sparc_reg_classes[CLASS_sparc_gp],
1121  .single_req = &sparc_single_reg_req_gp_i5,
1122  .index = REG_GP_I5,
1123  .global_index = REG_I5,
1124  .dwarf_number = 29,
1125  .encoding = 29,
1126  .is_virtual = false,
1127  },
1128  {
1129  .name = "fp",
1130  .cls = &sparc_reg_classes[CLASS_sparc_gp],
1131  .single_req = &sparc_single_reg_req_gp_fp,
1132  .index = REG_GP_FP,
1133  .global_index = REG_FP,
1134  .dwarf_number = 30,
1135  .encoding = 30,
1136  .is_virtual = false,
1137  },
1138  {
1139  .name = "i7",
1140  .cls = &sparc_reg_classes[CLASS_sparc_gp],
1141  .single_req = &sparc_single_reg_req_gp_i7,
1142  .index = REG_GP_I7,
1143  .global_index = REG_I7,
1144  .dwarf_number = 31,
1145  .encoding = 31,
1146  .is_virtual = false,
1147  },
1148  {
1149  .name = "y",
1150  .cls = &sparc_reg_classes[CLASS_sparc_mul_div_high_res],
1151  .single_req = &sparc_single_reg_req_mul_div_high_res_y,
1152  .index = REG_MUL_DIV_HIGH_RES_Y,
1153  .global_index = REG_Y,
1154  .dwarf_number = 0,
1155  .encoding = REG_MUL_DIV_HIGH_RES_Y,
1156  .is_virtual = false,
1157  },
1158 
1159 };
1160 
1164 void sparc_register_init(void)
1165 {
1166  sparc_reg_classes[CLASS_sparc_flags].mode = mode_Bu;
1167  sparc_reg_classes[CLASS_sparc_fp].mode = mode_F;
1168  sparc_reg_classes[CLASS_sparc_fpflags].mode = mode_Bu;
1169  sparc_reg_classes[CLASS_sparc_gp].mode = mode_Iu;
1170  sparc_reg_classes[CLASS_sparc_mul_div_high_res].mode = mode_Iu;
1171 
1172 }
ir_mode * mode_F
ieee754 binary32 float (single precision)
Definition: irmode.h:180
ir_mode * mode_Iu
uint32
Definition: irmode.h:187
ir_mode * mode_Bu
uint8
Definition: irmode.h:183