11 #include "gen_sparc_regalloc_if.h"
13 #include "sparc_bearch_t.h"
15 const arch_register_req_t sparc_class_reg_req_flags = {
16 .cls = &sparc_reg_classes[CLASS_sparc_flags],
19 static const unsigned sparc_limited_flags_psr[] = { (1U << REG_FLAGS_PSR) };
20 const arch_register_req_t sparc_single_reg_req_flags_psr = {
21 .cls = &sparc_reg_classes[CLASS_sparc_flags],
22 .limited = sparc_limited_flags_psr,
25 const arch_register_req_t sparc_class_reg_req_fp = {
26 .cls = &sparc_reg_classes[CLASS_sparc_fp],
29 static const unsigned sparc_limited_fp_f0[] = { (1U << REG_FP_F0) };
30 const arch_register_req_t sparc_single_reg_req_fp_f0 = {
31 .cls = &sparc_reg_classes[CLASS_sparc_fp],
32 .limited = sparc_limited_fp_f0,
35 static const unsigned sparc_limited_fp_f1[] = { (1U << REG_FP_F1) };
36 const arch_register_req_t sparc_single_reg_req_fp_f1 = {
37 .cls = &sparc_reg_classes[CLASS_sparc_fp],
38 .limited = sparc_limited_fp_f1,
41 static const unsigned sparc_limited_fp_f2[] = { (1U << REG_FP_F2) };
42 const arch_register_req_t sparc_single_reg_req_fp_f2 = {
43 .cls = &sparc_reg_classes[CLASS_sparc_fp],
44 .limited = sparc_limited_fp_f2,
47 static const unsigned sparc_limited_fp_f3[] = { (1U << REG_FP_F3) };
48 const arch_register_req_t sparc_single_reg_req_fp_f3 = {
49 .cls = &sparc_reg_classes[CLASS_sparc_fp],
50 .limited = sparc_limited_fp_f3,
53 static const unsigned sparc_limited_fp_f4[] = { (1U << REG_FP_F4) };
54 const arch_register_req_t sparc_single_reg_req_fp_f4 = {
55 .cls = &sparc_reg_classes[CLASS_sparc_fp],
56 .limited = sparc_limited_fp_f4,
59 static const unsigned sparc_limited_fp_f5[] = { (1U << REG_FP_F5) };
60 const arch_register_req_t sparc_single_reg_req_fp_f5 = {
61 .cls = &sparc_reg_classes[CLASS_sparc_fp],
62 .limited = sparc_limited_fp_f5,
65 static const unsigned sparc_limited_fp_f6[] = { (1U << REG_FP_F6) };
66 const arch_register_req_t sparc_single_reg_req_fp_f6 = {
67 .cls = &sparc_reg_classes[CLASS_sparc_fp],
68 .limited = sparc_limited_fp_f6,
71 static const unsigned sparc_limited_fp_f7[] = { (1U << REG_FP_F7) };
72 const arch_register_req_t sparc_single_reg_req_fp_f7 = {
73 .cls = &sparc_reg_classes[CLASS_sparc_fp],
74 .limited = sparc_limited_fp_f7,
77 static const unsigned sparc_limited_fp_f8[] = { (1U << REG_FP_F8) };
78 const arch_register_req_t sparc_single_reg_req_fp_f8 = {
79 .cls = &sparc_reg_classes[CLASS_sparc_fp],
80 .limited = sparc_limited_fp_f8,
83 static const unsigned sparc_limited_fp_f9[] = { (1U << REG_FP_F9) };
84 const arch_register_req_t sparc_single_reg_req_fp_f9 = {
85 .cls = &sparc_reg_classes[CLASS_sparc_fp],
86 .limited = sparc_limited_fp_f9,
89 static const unsigned sparc_limited_fp_f10[] = { (1U << REG_FP_F10) };
90 const arch_register_req_t sparc_single_reg_req_fp_f10 = {
91 .cls = &sparc_reg_classes[CLASS_sparc_fp],
92 .limited = sparc_limited_fp_f10,
95 static const unsigned sparc_limited_fp_f11[] = { (1U << REG_FP_F11) };
96 const arch_register_req_t sparc_single_reg_req_fp_f11 = {
97 .cls = &sparc_reg_classes[CLASS_sparc_fp],
98 .limited = sparc_limited_fp_f11,
101 static const unsigned sparc_limited_fp_f12[] = { (1U << REG_FP_F12) };
102 const arch_register_req_t sparc_single_reg_req_fp_f12 = {
103 .cls = &sparc_reg_classes[CLASS_sparc_fp],
104 .limited = sparc_limited_fp_f12,
107 static const unsigned sparc_limited_fp_f13[] = { (1U << REG_FP_F13) };
108 const arch_register_req_t sparc_single_reg_req_fp_f13 = {
109 .cls = &sparc_reg_classes[CLASS_sparc_fp],
110 .limited = sparc_limited_fp_f13,
113 static const unsigned sparc_limited_fp_f14[] = { (1U << REG_FP_F14) };
114 const arch_register_req_t sparc_single_reg_req_fp_f14 = {
115 .cls = &sparc_reg_classes[CLASS_sparc_fp],
116 .limited = sparc_limited_fp_f14,
119 static const unsigned sparc_limited_fp_f15[] = { (1U << REG_FP_F15) };
120 const arch_register_req_t sparc_single_reg_req_fp_f15 = {
121 .cls = &sparc_reg_classes[CLASS_sparc_fp],
122 .limited = sparc_limited_fp_f15,
125 static const unsigned sparc_limited_fp_f16[] = { (1U << REG_FP_F16) };
126 const arch_register_req_t sparc_single_reg_req_fp_f16 = {
127 .cls = &sparc_reg_classes[CLASS_sparc_fp],
128 .limited = sparc_limited_fp_f16,
131 static const unsigned sparc_limited_fp_f17[] = { (1U << REG_FP_F17) };
132 const arch_register_req_t sparc_single_reg_req_fp_f17 = {
133 .cls = &sparc_reg_classes[CLASS_sparc_fp],
134 .limited = sparc_limited_fp_f17,
137 static const unsigned sparc_limited_fp_f18[] = { (1U << REG_FP_F18) };
138 const arch_register_req_t sparc_single_reg_req_fp_f18 = {
139 .cls = &sparc_reg_classes[CLASS_sparc_fp],
140 .limited = sparc_limited_fp_f18,
143 static const unsigned sparc_limited_fp_f19[] = { (1U << REG_FP_F19) };
144 const arch_register_req_t sparc_single_reg_req_fp_f19 = {
145 .cls = &sparc_reg_classes[CLASS_sparc_fp],
146 .limited = sparc_limited_fp_f19,
149 static const unsigned sparc_limited_fp_f20[] = { (1U << REG_FP_F20) };
150 const arch_register_req_t sparc_single_reg_req_fp_f20 = {
151 .cls = &sparc_reg_classes[CLASS_sparc_fp],
152 .limited = sparc_limited_fp_f20,
155 static const unsigned sparc_limited_fp_f21[] = { (1U << REG_FP_F21) };
156 const arch_register_req_t sparc_single_reg_req_fp_f21 = {
157 .cls = &sparc_reg_classes[CLASS_sparc_fp],
158 .limited = sparc_limited_fp_f21,
161 static const unsigned sparc_limited_fp_f22[] = { (1U << REG_FP_F22) };
162 const arch_register_req_t sparc_single_reg_req_fp_f22 = {
163 .cls = &sparc_reg_classes[CLASS_sparc_fp],
164 .limited = sparc_limited_fp_f22,
167 static const unsigned sparc_limited_fp_f23[] = { (1U << REG_FP_F23) };
168 const arch_register_req_t sparc_single_reg_req_fp_f23 = {
169 .cls = &sparc_reg_classes[CLASS_sparc_fp],
170 .limited = sparc_limited_fp_f23,
173 static const unsigned sparc_limited_fp_f24[] = { (1U << REG_FP_F24) };
174 const arch_register_req_t sparc_single_reg_req_fp_f24 = {
175 .cls = &sparc_reg_classes[CLASS_sparc_fp],
176 .limited = sparc_limited_fp_f24,
179 static const unsigned sparc_limited_fp_f25[] = { (1U << REG_FP_F25) };
180 const arch_register_req_t sparc_single_reg_req_fp_f25 = {
181 .cls = &sparc_reg_classes[CLASS_sparc_fp],
182 .limited = sparc_limited_fp_f25,
185 static const unsigned sparc_limited_fp_f26[] = { (1U << REG_FP_F26) };
186 const arch_register_req_t sparc_single_reg_req_fp_f26 = {
187 .cls = &sparc_reg_classes[CLASS_sparc_fp],
188 .limited = sparc_limited_fp_f26,
191 static const unsigned sparc_limited_fp_f27[] = { (1U << REG_FP_F27) };
192 const arch_register_req_t sparc_single_reg_req_fp_f27 = {
193 .cls = &sparc_reg_classes[CLASS_sparc_fp],
194 .limited = sparc_limited_fp_f27,
197 static const unsigned sparc_limited_fp_f28[] = { (1U << REG_FP_F28) };
198 const arch_register_req_t sparc_single_reg_req_fp_f28 = {
199 .cls = &sparc_reg_classes[CLASS_sparc_fp],
200 .limited = sparc_limited_fp_f28,
203 static const unsigned sparc_limited_fp_f29[] = { (1U << REG_FP_F29) };
204 const arch_register_req_t sparc_single_reg_req_fp_f29 = {
205 .cls = &sparc_reg_classes[CLASS_sparc_fp],
206 .limited = sparc_limited_fp_f29,
209 static const unsigned sparc_limited_fp_f30[] = { (1U << REG_FP_F30) };
210 const arch_register_req_t sparc_single_reg_req_fp_f30 = {
211 .cls = &sparc_reg_classes[CLASS_sparc_fp],
212 .limited = sparc_limited_fp_f30,
215 static const unsigned sparc_limited_fp_f31[] = { (1U << REG_FP_F31) };
216 const arch_register_req_t sparc_single_reg_req_fp_f31 = {
217 .cls = &sparc_reg_classes[CLASS_sparc_fp],
218 .limited = sparc_limited_fp_f31,
221 const arch_register_req_t sparc_class_reg_req_fpflags = {
222 .cls = &sparc_reg_classes[CLASS_sparc_fpflags],
225 static const unsigned sparc_limited_fpflags_fsr[] = { (1U << REG_FPFLAGS_FSR) };
226 const arch_register_req_t sparc_single_reg_req_fpflags_fsr = {
227 .cls = &sparc_reg_classes[CLASS_sparc_fpflags],
228 .limited = sparc_limited_fpflags_fsr,
231 const arch_register_req_t sparc_class_reg_req_gp = {
232 .cls = &sparc_reg_classes[CLASS_sparc_gp],
235 static const unsigned sparc_limited_gp_l0[] = { (1U << REG_GP_L0) };
236 const arch_register_req_t sparc_single_reg_req_gp_l0 = {
237 .cls = &sparc_reg_classes[CLASS_sparc_gp],
238 .limited = sparc_limited_gp_l0,
241 static const unsigned sparc_limited_gp_l1[] = { (1U << REG_GP_L1) };
242 const arch_register_req_t sparc_single_reg_req_gp_l1 = {
243 .cls = &sparc_reg_classes[CLASS_sparc_gp],
244 .limited = sparc_limited_gp_l1,
247 static const unsigned sparc_limited_gp_l2[] = { (1U << REG_GP_L2) };
248 const arch_register_req_t sparc_single_reg_req_gp_l2 = {
249 .cls = &sparc_reg_classes[CLASS_sparc_gp],
250 .limited = sparc_limited_gp_l2,
253 static const unsigned sparc_limited_gp_l3[] = { (1U << REG_GP_L3) };
254 const arch_register_req_t sparc_single_reg_req_gp_l3 = {
255 .cls = &sparc_reg_classes[CLASS_sparc_gp],
256 .limited = sparc_limited_gp_l3,
259 static const unsigned sparc_limited_gp_l4[] = { (1U << REG_GP_L4) };
260 const arch_register_req_t sparc_single_reg_req_gp_l4 = {
261 .cls = &sparc_reg_classes[CLASS_sparc_gp],
262 .limited = sparc_limited_gp_l4,
265 static const unsigned sparc_limited_gp_l5[] = { (1U << REG_GP_L5) };
266 const arch_register_req_t sparc_single_reg_req_gp_l5 = {
267 .cls = &sparc_reg_classes[CLASS_sparc_gp],
268 .limited = sparc_limited_gp_l5,
271 static const unsigned sparc_limited_gp_l6[] = { (1U << REG_GP_L6) };
272 const arch_register_req_t sparc_single_reg_req_gp_l6 = {
273 .cls = &sparc_reg_classes[CLASS_sparc_gp],
274 .limited = sparc_limited_gp_l6,
277 static const unsigned sparc_limited_gp_l7[] = { (1U << REG_GP_L7) };
278 const arch_register_req_t sparc_single_reg_req_gp_l7 = {
279 .cls = &sparc_reg_classes[CLASS_sparc_gp],
280 .limited = sparc_limited_gp_l7,
283 static const unsigned sparc_limited_gp_g0[] = { (1U << REG_GP_G0) };
284 const arch_register_req_t sparc_single_reg_req_gp_g0 = {
285 .cls = &sparc_reg_classes[CLASS_sparc_gp],
286 .limited = sparc_limited_gp_g0,
289 static const unsigned sparc_limited_gp_g1[] = { (1U << REG_GP_G1) };
290 const arch_register_req_t sparc_single_reg_req_gp_g1 = {
291 .cls = &sparc_reg_classes[CLASS_sparc_gp],
292 .limited = sparc_limited_gp_g1,
295 static const unsigned sparc_limited_gp_g2[] = { (1U << REG_GP_G2) };
296 const arch_register_req_t sparc_single_reg_req_gp_g2 = {
297 .cls = &sparc_reg_classes[CLASS_sparc_gp],
298 .limited = sparc_limited_gp_g2,
301 static const unsigned sparc_limited_gp_g3[] = { (1U << REG_GP_G3) };
302 const arch_register_req_t sparc_single_reg_req_gp_g3 = {
303 .cls = &sparc_reg_classes[CLASS_sparc_gp],
304 .limited = sparc_limited_gp_g3,
307 static const unsigned sparc_limited_gp_g4[] = { (1U << REG_GP_G4) };
308 const arch_register_req_t sparc_single_reg_req_gp_g4 = {
309 .cls = &sparc_reg_classes[CLASS_sparc_gp],
310 .limited = sparc_limited_gp_g4,
313 static const unsigned sparc_limited_gp_g5[] = { (1U << REG_GP_G5) };
314 const arch_register_req_t sparc_single_reg_req_gp_g5 = {
315 .cls = &sparc_reg_classes[CLASS_sparc_gp],
316 .limited = sparc_limited_gp_g5,
319 static const unsigned sparc_limited_gp_g6[] = { (1U << REG_GP_G6) };
320 const arch_register_req_t sparc_single_reg_req_gp_g6 = {
321 .cls = &sparc_reg_classes[CLASS_sparc_gp],
322 .limited = sparc_limited_gp_g6,
325 static const unsigned sparc_limited_gp_g7[] = { (1U << REG_GP_G7) };
326 const arch_register_req_t sparc_single_reg_req_gp_g7 = {
327 .cls = &sparc_reg_classes[CLASS_sparc_gp],
328 .limited = sparc_limited_gp_g7,
331 static const unsigned sparc_limited_gp_o0[] = { (1U << REG_GP_O0) };
332 const arch_register_req_t sparc_single_reg_req_gp_o0 = {
333 .cls = &sparc_reg_classes[CLASS_sparc_gp],
334 .limited = sparc_limited_gp_o0,
337 static const unsigned sparc_limited_gp_o1[] = { (1U << REG_GP_O1) };
338 const arch_register_req_t sparc_single_reg_req_gp_o1 = {
339 .cls = &sparc_reg_classes[CLASS_sparc_gp],
340 .limited = sparc_limited_gp_o1,
343 static const unsigned sparc_limited_gp_o2[] = { (1U << REG_GP_O2) };
344 const arch_register_req_t sparc_single_reg_req_gp_o2 = {
345 .cls = &sparc_reg_classes[CLASS_sparc_gp],
346 .limited = sparc_limited_gp_o2,
349 static const unsigned sparc_limited_gp_o3[] = { (1U << REG_GP_O3) };
350 const arch_register_req_t sparc_single_reg_req_gp_o3 = {
351 .cls = &sparc_reg_classes[CLASS_sparc_gp],
352 .limited = sparc_limited_gp_o3,
355 static const unsigned sparc_limited_gp_o4[] = { (1U << REG_GP_O4) };
356 const arch_register_req_t sparc_single_reg_req_gp_o4 = {
357 .cls = &sparc_reg_classes[CLASS_sparc_gp],
358 .limited = sparc_limited_gp_o4,
361 static const unsigned sparc_limited_gp_o5[] = { (1U << REG_GP_O5) };
362 const arch_register_req_t sparc_single_reg_req_gp_o5 = {
363 .cls = &sparc_reg_classes[CLASS_sparc_gp],
364 .limited = sparc_limited_gp_o5,
367 static const unsigned sparc_limited_gp_sp[] = { (1U << REG_GP_SP) };
368 const arch_register_req_t sparc_single_reg_req_gp_sp = {
369 .cls = &sparc_reg_classes[CLASS_sparc_gp],
370 .limited = sparc_limited_gp_sp,
373 static const unsigned sparc_limited_gp_o7[] = { (1U << REG_GP_O7) };
374 const arch_register_req_t sparc_single_reg_req_gp_o7 = {
375 .cls = &sparc_reg_classes[CLASS_sparc_gp],
376 .limited = sparc_limited_gp_o7,
379 static const unsigned sparc_limited_gp_i0[] = { (1U << REG_GP_I0) };
380 const arch_register_req_t sparc_single_reg_req_gp_i0 = {
381 .cls = &sparc_reg_classes[CLASS_sparc_gp],
382 .limited = sparc_limited_gp_i0,
385 static const unsigned sparc_limited_gp_i1[] = { (1U << REG_GP_I1) };
386 const arch_register_req_t sparc_single_reg_req_gp_i1 = {
387 .cls = &sparc_reg_classes[CLASS_sparc_gp],
388 .limited = sparc_limited_gp_i1,
391 static const unsigned sparc_limited_gp_i2[] = { (1U << REG_GP_I2) };
392 const arch_register_req_t sparc_single_reg_req_gp_i2 = {
393 .cls = &sparc_reg_classes[CLASS_sparc_gp],
394 .limited = sparc_limited_gp_i2,
397 static const unsigned sparc_limited_gp_i3[] = { (1U << REG_GP_I3) };
398 const arch_register_req_t sparc_single_reg_req_gp_i3 = {
399 .cls = &sparc_reg_classes[CLASS_sparc_gp],
400 .limited = sparc_limited_gp_i3,
403 static const unsigned sparc_limited_gp_i4[] = { (1U << REG_GP_I4) };
404 const arch_register_req_t sparc_single_reg_req_gp_i4 = {
405 .cls = &sparc_reg_classes[CLASS_sparc_gp],
406 .limited = sparc_limited_gp_i4,
409 static const unsigned sparc_limited_gp_i5[] = { (1U << REG_GP_I5) };
410 const arch_register_req_t sparc_single_reg_req_gp_i5 = {
411 .cls = &sparc_reg_classes[CLASS_sparc_gp],
412 .limited = sparc_limited_gp_i5,
415 static const unsigned sparc_limited_gp_fp[] = { (1U << REG_GP_FP) };
416 const arch_register_req_t sparc_single_reg_req_gp_fp = {
417 .cls = &sparc_reg_classes[CLASS_sparc_gp],
418 .limited = sparc_limited_gp_fp,
421 static const unsigned sparc_limited_gp_i7[] = { (1U << REG_GP_I7) };
422 const arch_register_req_t sparc_single_reg_req_gp_i7 = {
423 .cls = &sparc_reg_classes[CLASS_sparc_gp],
424 .limited = sparc_limited_gp_i7,
427 const arch_register_req_t sparc_class_reg_req_mul_div_high_res = {
428 .cls = &sparc_reg_classes[CLASS_sparc_mul_div_high_res],
431 static const unsigned sparc_limited_mul_div_high_res_y[] = { (1U << REG_MUL_DIV_HIGH_RES_Y) };
432 const arch_register_req_t sparc_single_reg_req_mul_div_high_res_y = {
433 .cls = &sparc_reg_classes[CLASS_sparc_mul_div_high_res],
434 .limited = sparc_limited_mul_div_high_res_y,
439 arch_register_class_t sparc_reg_classes[] = {
441 .name =
"sparc_flags",
443 .regs = &sparc_registers[REG_PSR],
444 .class_req = &sparc_class_reg_req_flags,
445 .index = CLASS_sparc_flags,
452 .regs = &sparc_registers[REG_F0],
453 .class_req = &sparc_class_reg_req_fp,
454 .index = CLASS_sparc_fp,
458 .name =
"sparc_fpflags",
460 .regs = &sparc_registers[REG_FSR],
461 .class_req = &sparc_class_reg_req_fpflags,
462 .index = CLASS_sparc_fpflags,
469 .regs = &sparc_registers[REG_L0],
470 .class_req = &sparc_class_reg_req_gp,
471 .index = CLASS_sparc_gp,
475 .name =
"sparc_mul_div_high_res",
477 .regs = &sparc_registers[REG_Y],
478 .class_req = &sparc_class_reg_req_mul_div_high_res,
479 .index = CLASS_sparc_mul_div_high_res,
487 const arch_register_t sparc_registers[] = {
490 .cls = &sparc_reg_classes[CLASS_sparc_flags],
491 .single_req = &sparc_single_reg_req_flags_psr,
492 .index = REG_FLAGS_PSR,
493 .global_index = REG_PSR,
495 .encoding = REG_FLAGS_PSR,
500 .cls = &sparc_reg_classes[CLASS_sparc_fp],
501 .single_req = &sparc_single_reg_req_fp_f0,
503 .global_index = REG_F0,
510 .cls = &sparc_reg_classes[CLASS_sparc_fp],
511 .single_req = &sparc_single_reg_req_fp_f1,
513 .global_index = REG_F1,
520 .cls = &sparc_reg_classes[CLASS_sparc_fp],
521 .single_req = &sparc_single_reg_req_fp_f2,
523 .global_index = REG_F2,
530 .cls = &sparc_reg_classes[CLASS_sparc_fp],
531 .single_req = &sparc_single_reg_req_fp_f3,
533 .global_index = REG_F3,
540 .cls = &sparc_reg_classes[CLASS_sparc_fp],
541 .single_req = &sparc_single_reg_req_fp_f4,
543 .global_index = REG_F4,
550 .cls = &sparc_reg_classes[CLASS_sparc_fp],
551 .single_req = &sparc_single_reg_req_fp_f5,
553 .global_index = REG_F5,
560 .cls = &sparc_reg_classes[CLASS_sparc_fp],
561 .single_req = &sparc_single_reg_req_fp_f6,
563 .global_index = REG_F6,
570 .cls = &sparc_reg_classes[CLASS_sparc_fp],
571 .single_req = &sparc_single_reg_req_fp_f7,
573 .global_index = REG_F7,
580 .cls = &sparc_reg_classes[CLASS_sparc_fp],
581 .single_req = &sparc_single_reg_req_fp_f8,
583 .global_index = REG_F8,
590 .cls = &sparc_reg_classes[CLASS_sparc_fp],
591 .single_req = &sparc_single_reg_req_fp_f9,
593 .global_index = REG_F9,
600 .cls = &sparc_reg_classes[CLASS_sparc_fp],
601 .single_req = &sparc_single_reg_req_fp_f10,
603 .global_index = REG_F10,
610 .cls = &sparc_reg_classes[CLASS_sparc_fp],
611 .single_req = &sparc_single_reg_req_fp_f11,
613 .global_index = REG_F11,
620 .cls = &sparc_reg_classes[CLASS_sparc_fp],
621 .single_req = &sparc_single_reg_req_fp_f12,
623 .global_index = REG_F12,
630 .cls = &sparc_reg_classes[CLASS_sparc_fp],
631 .single_req = &sparc_single_reg_req_fp_f13,
633 .global_index = REG_F13,
640 .cls = &sparc_reg_classes[CLASS_sparc_fp],
641 .single_req = &sparc_single_reg_req_fp_f14,
643 .global_index = REG_F14,
650 .cls = &sparc_reg_classes[CLASS_sparc_fp],
651 .single_req = &sparc_single_reg_req_fp_f15,
653 .global_index = REG_F15,
660 .cls = &sparc_reg_classes[CLASS_sparc_fp],
661 .single_req = &sparc_single_reg_req_fp_f16,
663 .global_index = REG_F16,
670 .cls = &sparc_reg_classes[CLASS_sparc_fp],
671 .single_req = &sparc_single_reg_req_fp_f17,
673 .global_index = REG_F17,
680 .cls = &sparc_reg_classes[CLASS_sparc_fp],
681 .single_req = &sparc_single_reg_req_fp_f18,
683 .global_index = REG_F18,
690 .cls = &sparc_reg_classes[CLASS_sparc_fp],
691 .single_req = &sparc_single_reg_req_fp_f19,
693 .global_index = REG_F19,
700 .cls = &sparc_reg_classes[CLASS_sparc_fp],
701 .single_req = &sparc_single_reg_req_fp_f20,
703 .global_index = REG_F20,
710 .cls = &sparc_reg_classes[CLASS_sparc_fp],
711 .single_req = &sparc_single_reg_req_fp_f21,
713 .global_index = REG_F21,
720 .cls = &sparc_reg_classes[CLASS_sparc_fp],
721 .single_req = &sparc_single_reg_req_fp_f22,
723 .global_index = REG_F22,
730 .cls = &sparc_reg_classes[CLASS_sparc_fp],
731 .single_req = &sparc_single_reg_req_fp_f23,
733 .global_index = REG_F23,
740 .cls = &sparc_reg_classes[CLASS_sparc_fp],
741 .single_req = &sparc_single_reg_req_fp_f24,
743 .global_index = REG_F24,
750 .cls = &sparc_reg_classes[CLASS_sparc_fp],
751 .single_req = &sparc_single_reg_req_fp_f25,
753 .global_index = REG_F25,
760 .cls = &sparc_reg_classes[CLASS_sparc_fp],
761 .single_req = &sparc_single_reg_req_fp_f26,
763 .global_index = REG_F26,
770 .cls = &sparc_reg_classes[CLASS_sparc_fp],
771 .single_req = &sparc_single_reg_req_fp_f27,
773 .global_index = REG_F27,
780 .cls = &sparc_reg_classes[CLASS_sparc_fp],
781 .single_req = &sparc_single_reg_req_fp_f28,
783 .global_index = REG_F28,
790 .cls = &sparc_reg_classes[CLASS_sparc_fp],
791 .single_req = &sparc_single_reg_req_fp_f29,
793 .global_index = REG_F29,
800 .cls = &sparc_reg_classes[CLASS_sparc_fp],
801 .single_req = &sparc_single_reg_req_fp_f30,
803 .global_index = REG_F30,
810 .cls = &sparc_reg_classes[CLASS_sparc_fp],
811 .single_req = &sparc_single_reg_req_fp_f31,
813 .global_index = REG_F31,
820 .cls = &sparc_reg_classes[CLASS_sparc_fpflags],
821 .single_req = &sparc_single_reg_req_fpflags_fsr,
822 .index = REG_FPFLAGS_FSR,
823 .global_index = REG_FSR,
825 .encoding = REG_FPFLAGS_FSR,
830 .cls = &sparc_reg_classes[CLASS_sparc_gp],
831 .single_req = &sparc_single_reg_req_gp_l0,
833 .global_index = REG_L0,
840 .cls = &sparc_reg_classes[CLASS_sparc_gp],
841 .single_req = &sparc_single_reg_req_gp_l1,
843 .global_index = REG_L1,
850 .cls = &sparc_reg_classes[CLASS_sparc_gp],
851 .single_req = &sparc_single_reg_req_gp_l2,
853 .global_index = REG_L2,
860 .cls = &sparc_reg_classes[CLASS_sparc_gp],
861 .single_req = &sparc_single_reg_req_gp_l3,
863 .global_index = REG_L3,
870 .cls = &sparc_reg_classes[CLASS_sparc_gp],
871 .single_req = &sparc_single_reg_req_gp_l4,
873 .global_index = REG_L4,
880 .cls = &sparc_reg_classes[CLASS_sparc_gp],
881 .single_req = &sparc_single_reg_req_gp_l5,
883 .global_index = REG_L5,
890 .cls = &sparc_reg_classes[CLASS_sparc_gp],
891 .single_req = &sparc_single_reg_req_gp_l6,
893 .global_index = REG_L6,
900 .cls = &sparc_reg_classes[CLASS_sparc_gp],
901 .single_req = &sparc_single_reg_req_gp_l7,
903 .global_index = REG_L7,
910 .cls = &sparc_reg_classes[CLASS_sparc_gp],
911 .single_req = &sparc_single_reg_req_gp_g0,
913 .global_index = REG_G0,
920 .cls = &sparc_reg_classes[CLASS_sparc_gp],
921 .single_req = &sparc_single_reg_req_gp_g1,
923 .global_index = REG_G1,
930 .cls = &sparc_reg_classes[CLASS_sparc_gp],
931 .single_req = &sparc_single_reg_req_gp_g2,
933 .global_index = REG_G2,
940 .cls = &sparc_reg_classes[CLASS_sparc_gp],
941 .single_req = &sparc_single_reg_req_gp_g3,
943 .global_index = REG_G3,
950 .cls = &sparc_reg_classes[CLASS_sparc_gp],
951 .single_req = &sparc_single_reg_req_gp_g4,
953 .global_index = REG_G4,
960 .cls = &sparc_reg_classes[CLASS_sparc_gp],
961 .single_req = &sparc_single_reg_req_gp_g5,
963 .global_index = REG_G5,
970 .cls = &sparc_reg_classes[CLASS_sparc_gp],
971 .single_req = &sparc_single_reg_req_gp_g6,
973 .global_index = REG_G6,
980 .cls = &sparc_reg_classes[CLASS_sparc_gp],
981 .single_req = &sparc_single_reg_req_gp_g7,
983 .global_index = REG_G7,
990 .cls = &sparc_reg_classes[CLASS_sparc_gp],
991 .single_req = &sparc_single_reg_req_gp_o0,
993 .global_index = REG_O0,
1000 .cls = &sparc_reg_classes[CLASS_sparc_gp],
1001 .single_req = &sparc_single_reg_req_gp_o1,
1003 .global_index = REG_O1,
1006 .is_virtual =
false,
1010 .cls = &sparc_reg_classes[CLASS_sparc_gp],
1011 .single_req = &sparc_single_reg_req_gp_o2,
1013 .global_index = REG_O2,
1016 .is_virtual =
false,
1020 .cls = &sparc_reg_classes[CLASS_sparc_gp],
1021 .single_req = &sparc_single_reg_req_gp_o3,
1023 .global_index = REG_O3,
1026 .is_virtual =
false,
1030 .cls = &sparc_reg_classes[CLASS_sparc_gp],
1031 .single_req = &sparc_single_reg_req_gp_o4,
1033 .global_index = REG_O4,
1036 .is_virtual =
false,
1040 .cls = &sparc_reg_classes[CLASS_sparc_gp],
1041 .single_req = &sparc_single_reg_req_gp_o5,
1043 .global_index = REG_O5,
1046 .is_virtual =
false,
1050 .cls = &sparc_reg_classes[CLASS_sparc_gp],
1051 .single_req = &sparc_single_reg_req_gp_sp,
1053 .global_index = REG_SP,
1056 .is_virtual =
false,
1060 .cls = &sparc_reg_classes[CLASS_sparc_gp],
1061 .single_req = &sparc_single_reg_req_gp_o7,
1063 .global_index = REG_O7,
1066 .is_virtual =
false,
1070 .cls = &sparc_reg_classes[CLASS_sparc_gp],
1071 .single_req = &sparc_single_reg_req_gp_i0,
1073 .global_index = REG_I0,
1076 .is_virtual =
false,
1080 .cls = &sparc_reg_classes[CLASS_sparc_gp],
1081 .single_req = &sparc_single_reg_req_gp_i1,
1083 .global_index = REG_I1,
1086 .is_virtual =
false,
1090 .cls = &sparc_reg_classes[CLASS_sparc_gp],
1091 .single_req = &sparc_single_reg_req_gp_i2,
1093 .global_index = REG_I2,
1096 .is_virtual =
false,
1100 .cls = &sparc_reg_classes[CLASS_sparc_gp],
1101 .single_req = &sparc_single_reg_req_gp_i3,
1103 .global_index = REG_I3,
1106 .is_virtual =
false,
1110 .cls = &sparc_reg_classes[CLASS_sparc_gp],
1111 .single_req = &sparc_single_reg_req_gp_i4,
1113 .global_index = REG_I4,
1116 .is_virtual =
false,
1120 .cls = &sparc_reg_classes[CLASS_sparc_gp],
1121 .single_req = &sparc_single_reg_req_gp_i5,
1123 .global_index = REG_I5,
1126 .is_virtual =
false,
1130 .cls = &sparc_reg_classes[CLASS_sparc_gp],
1131 .single_req = &sparc_single_reg_req_gp_fp,
1133 .global_index = REG_FP,
1136 .is_virtual =
false,
1140 .cls = &sparc_reg_classes[CLASS_sparc_gp],
1141 .single_req = &sparc_single_reg_req_gp_i7,
1143 .global_index = REG_I7,
1146 .is_virtual =
false,
1150 .cls = &sparc_reg_classes[CLASS_sparc_mul_div_high_res],
1151 .single_req = &sparc_single_reg_req_mul_div_high_res_y,
1152 .index = REG_MUL_DIV_HIGH_RES_Y,
1153 .global_index = REG_Y,
1155 .encoding = REG_MUL_DIV_HIGH_RES_Y,
1156 .is_virtual =
false,
1164 void sparc_register_init(
void)
1166 sparc_reg_classes[CLASS_sparc_flags].mode =
mode_Bu;
1167 sparc_reg_classes[CLASS_sparc_fp].mode =
mode_F;
1168 sparc_reg_classes[CLASS_sparc_fpflags].mode =
mode_Bu;
1169 sparc_reg_classes[CLASS_sparc_gp].mode =
mode_Iu;
1170 sparc_reg_classes[CLASS_sparc_mul_div_high_res].mode =
mode_Iu;
ir_mode * mode_F
ieee754 binary32 float (single precision)